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target/ppc: Implement Vector Compare Quadword

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Implement the following PowerISA v3.1 instructions:
vcmpsq: Vector Compare Signed Quadword
vcmpuq: Vector Compare Unsigned Quadword

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220225210936.1749575-14-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
This commit is contained in:
Matheus Ferst 2022-03-02 06:51:37 +01:00 committed by Cédric Le Goater
parent 50449ae482
commit b58f393198
2 changed files with 51 additions and 0 deletions
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6
target/ppc/insn32.decode
View File

@ -60,6 +60,9 @@
&VX vrt vra vrb
@VX ...... vrt:5 vra:5 vrb:5 .......... . &VX
&VX_bf bf vra vrb
@VX_bf ...... bf:3 .. vra:5 vrb:5 ........... &VX_bf
&VX_uim4 vrt uim vrb
@VX_uim4 ...... vrt:5 . uim:4 vrb:5 ........... &VX_uim4
@ -404,6 +407,9 @@ VCMPNEZB 000100 ..... ..... ..... . 0100000111 @VC
VCMPNEZH 000100 ..... ..... ..... . 0101000111 @VC
VCMPNEZW 000100 ..... ..... ..... . 0110000111 @VC
VCMPSQ 000100 ... -- ..... ..... 00101000001 @VX_bf
VCMPUQ 000100 ... -- ..... ..... 00100000001 @VX_bf
## Vector Bit Manipulation Instruction
VCFUGED 000100 ..... ..... ..... 10101001101 @VX

45
target/ppc/translate/vmx-impl.c.inc
View File

@ -1182,6 +1182,51 @@ static bool do_vcmpgtq(DisasContext *ctx, arg_VC *a, bool sign)
TRANS(VCMPGTSQ, do_vcmpgtq, true)
TRANS(VCMPGTUQ, do_vcmpgtq, false)
static bool do_vcmpq(DisasContext *ctx, arg_VX_bf *a, bool sign)
{
TCGv_i64 vra, vrb;
TCGLabel *gt, *lt, *done;
REQUIRE_INSNS_FLAGS2(ctx, ISA310);
REQUIRE_VECTOR(ctx);
vra = tcg_temp_local_new_i64();
vrb = tcg_temp_local_new_i64();
gt = gen_new_label();
lt = gen_new_label();
done = gen_new_label();
get_avr64(vra, a->vra, true);
get_avr64(vrb, a->vrb, true);
tcg_gen_brcond_i64((sign ? TCG_COND_GT : TCG_COND_GTU), vra, vrb, gt);
tcg_gen_brcond_i64((sign ? TCG_COND_LT : TCG_COND_LTU), vra, vrb, lt);
get_avr64(vra, a->vra, false);
get_avr64(vrb, a->vrb, false);
tcg_gen_brcond_i64(TCG_COND_GTU, vra, vrb, gt);
tcg_gen_brcond_i64(TCG_COND_LTU, vra, vrb, lt);
tcg_gen_movi_i32(cpu_crf[a->bf], CRF_EQ);
tcg_gen_br(done);
gen_set_label(gt);
tcg_gen_movi_i32(cpu_crf[a->bf], CRF_GT);
tcg_gen_br(done);
gen_set_label(lt);
tcg_gen_movi_i32(cpu_crf[a->bf], CRF_LT);
tcg_gen_br(done);
gen_set_label(done);
tcg_temp_free_i64(vra);
tcg_temp_free_i64(vrb);
return true;
}
TRANS(VCMPSQ, do_vcmpq, true)
TRANS(VCMPUQ, do_vcmpq, false)
GEN_VXRFORM(vcmpeqfp, 3, 3)
GEN_VXRFORM(vcmpgefp, 3, 7)
GEN_VXRFORM(vcmpgtfp, 3, 11)