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RISC-V: XTheadMemPair: Remove register restrictions for store-pair

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The XTheadMemPair does not define any restrictions for store-pair
instructions (th.sdd or th.swd). However, the current code enforces
the restrictions that are required for load-pair instructions.
Let's fix this by removing this code.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20230220095612.1529031-1-christoph.muellner@vrull.eu>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
This commit is contained in:
Christoph Müllner 2023-02-20 10:56:12 +01:00 committed by Palmer Dabbelt
parent ae9c326fb6
commit b7fa70e2af
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1 changed files with 0 additions and 4 deletions
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target/riscv/insn_trans/trans_xthead.c.inc
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@ -980,10 +980,6 @@ static bool trans_th_lwud(DisasContext *ctx, arg_th_pair *a)
static bool gen_storepair_tl(DisasContext *ctx, arg_th_pair *a, MemOp memop,
int shamt)
{
if (a->rs == a->rd1 || a->rs == a->rd2 || a->rd1 == a->rd2) {
return false;
}
TCGv data1 = get_gpr(ctx, a->rd1, EXT_NONE);
TCGv data2 = get_gpr(ctx, a->rd2, EXT_NONE);
TCGv addr1 = tcg_temp_new();