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target/sparc: Move FMOVS, FNEGS, FABSS, FSRC*S, FNOT*S to decodetree 

Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-10-05 09:41:05 -07:00
parent 39ca3490f8
commit baf3dbf258
2 changed files with 62 additions and 43 deletions
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13
target/sparc/insns.decode
View File

@ -38,6 +38,10 @@ CALL 01 i:s30
&r_r_r rd rs1 rs2
@r_r_r .. rd:5 ...... rs1:5 . ........ rs2:5 &r_r_r
&r_r rd rs
@r_r1 .. rd:5 ...... rs:5 . ........ ..... &r_r
@r_r2 .. rd:5 ...... ..... . ........ rs:5 &r_r
{
[
STBAR 10 00000 101000 01111 0 0000000000000
@ -234,6 +238,10 @@ RESTORE 10 ..... 111101 ..... . ............. @r_r_ri
DONE 10 00000 111110 00000 0 0000000000000
RETRY 10 00001 111110 00000 0 0000000000000
FMOVs 10 ..... 110100 00000 0 0000 0001 ..... @r_r2
FNEGs 10 ..... 110100 00000 0 0000 0101 ..... @r_r2
FABSs 10 ..... 110100 00000 0 0000 1001 ..... @r_r2
{
[
EDGE8cc 10 ..... 110110 ..... 0 0000 0000 ..... @r_r_r
@ -257,6 +265,11 @@ RETRY 10 00001 111110 00000 0 0000000000000
ALIGNADDRL 10 ..... 110110 ..... 0 0001 1010 ..... @r_r_r
BMASK 10 ..... 110110 ..... 0 0001 1001 ..... @r_r_r
FSRCs 10 ..... 110110 ..... 0 0111 0101 00000 @r_r1 # FSRC1s
FSRCs 10 ..... 110110 00000 0 0111 1001 ..... @r_r2 # FSRC2s
FNOTs 10 ..... 110110 ..... 0 0110 1011 00000 @r_r1 # FNOT1s
FNOTs 10 ..... 110110 00000 0 0110 0111 ..... @r_r2 # FNOT2s
]
NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1
}

92
target/sparc/translate.c
View File

@ -1397,6 +1397,29 @@ static void gen_compare_reg(DisasCompare *cmp, int cond, TCGv r_src)
cmp->c2 = tcg_constant_tl(0);
}
static void gen_op_clear_ieee_excp_and_FTT(void)
{
tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_CEXC_NMASK);
}
static void gen_op_fmovs(TCGv_i32 dst, TCGv_i32 src)
{
gen_op_clear_ieee_excp_and_FTT();
tcg_gen_mov_i32(dst, src);
}
static void gen_op_fnegs(TCGv_i32 dst, TCGv_i32 src)
{
gen_op_clear_ieee_excp_and_FTT();
gen_helper_fnegs(dst, src);
}
static void gen_op_fabss(TCGv_i32 dst, TCGv_i32 src)
{
gen_op_clear_ieee_excp_and_FTT();
gen_helper_fabss(dst, src);
}
#ifdef TARGET_SPARC64
static void gen_op_fcmps(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2)
{
@ -1557,11 +1580,6 @@ static int gen_trap_ifnofpu(DisasContext *dc)
return 0;
}
static void gen_op_clear_ieee_excp_and_FTT(void)
{
tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_CEXC_NMASK);
}
static void gen_fop_FF(DisasContext *dc, int rd, int rs,
void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i32))
{
@ -1576,19 +1594,6 @@ static void gen_fop_FF(DisasContext *dc, int rd, int rs,
gen_store_fpr_F(dc, rd, dst);
}
static void gen_ne_fop_FF(DisasContext *dc, int rd, int rs,
void (*gen)(TCGv_i32, TCGv_i32))
{
TCGv_i32 dst, src;
src = gen_load_fpr_F(dc, rs);
dst = gen_dest_fpr_F(dc);
gen(dst, src);
gen_store_fpr_F(dc, rd, dst);
}
static void gen_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2,
void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32))
{
@ -4803,6 +4808,27 @@ static bool do_stfsr(DisasContext *dc, arg_r_r_ri *a, MemOp mop)
TRANS(STFSR, ALL, do_stfsr, a, MO_TEUL)
TRANS(STXFSR, 64, do_stfsr, a, MO_TEUQ)
static bool do_ff(DisasContext *dc, arg_r_r *a,
void (*func)(TCGv_i32, TCGv_i32))
{
TCGv_i32 tmp;
if (gen_trap_ifnofpu(dc)) {
return true;
}
tmp = gen_load_fpr_F(dc, a->rs);
func(tmp, tmp);
gen_store_fpr_F(dc, a->rd, tmp);
return advance_pc(dc);
}
TRANS(FMOVs, ALL, do_ff, a, gen_op_fmovs)
TRANS(FNEGs, ALL, do_ff, a, gen_op_fnegs)
TRANS(FABSs, ALL, do_ff, a, gen_op_fabss)
TRANS(FSRCs, VIS1, do_ff, a, tcg_gen_mov_i32)
TRANS(FNOTs, VIS1, do_ff, a, tcg_gen_not_i32)
#define CHECK_IU_FEATURE(dc, FEATURE) \
if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
goto illegal_insn;
@ -4844,15 +4870,9 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
switch (xop) {
case 0x1: /* fmovs */
cpu_src1_32 = gen_load_fpr_F(dc, rs2);
gen_store_fpr_F(dc, rd, cpu_src1_32);
break;
case 0x5: /* fnegs */
gen_ne_fop_FF(dc, rd, rs2, gen_helper_fnegs);
break;
case 0x9: /* fabss */
gen_ne_fop_FF(dc, rd, rs2, gen_helper_fabss);
break;
g_assert_not_reached(); /* in decodetree */
case 0x29: /* fsqrts */
gen_fop_FF(dc, rd, rs2, gen_helper_fsqrts);
break;
@ -5180,6 +5200,10 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
case 0x018: /* VIS I alignaddr */
case 0x01a: /* VIS I alignaddrl */
case 0x019: /* VIS II bmask */
case 0x067: /* VIS I fnot2s */
case 0x06b: /* VIS I fnot1s */
case 0x075: /* VIS I fsrc1s */
case 0x079: /* VIS I fsrc2s */
g_assert_not_reached(); /* in decodetree */
case 0x020: /* VIS I fcmple16 */
CHECK_FPU_FEATURE(dc, VIS1);
@ -5367,10 +5391,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
CHECK_FPU_FEATURE(dc, VIS1);
gen_ne_fop_DD(dc, rd, rs2, tcg_gen_not_i64);
break;
case 0x067: /* VIS I fnot2s */
CHECK_FPU_FEATURE(dc, VIS1);
gen_ne_fop_FF(dc, rd, rs2, tcg_gen_not_i32);
break;
case 0x068: /* VIS I fandnot1 */
CHECK_FPU_FEATURE(dc, VIS1);
gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_andc_i64);
@ -5383,10 +5403,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
CHECK_FPU_FEATURE(dc, VIS1);
gen_ne_fop_DD(dc, rd, rs1, tcg_gen_not_i64);
break;
case 0x06b: /* VIS I fnot1s */
CHECK_FPU_FEATURE(dc, VIS1);
gen_ne_fop_FF(dc, rd, rs1, tcg_gen_not_i32);
break;
case 0x06c: /* VIS I fxor */
CHECK_FPU_FEATURE(dc, VIS1);
gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_xor_i64);
@ -5424,11 +5440,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
cpu_src1_64 = gen_load_fpr_D(dc, rs1);
gen_store_fpr_D(dc, rd, cpu_src1_64);
break;
case 0x075: /* VIS I fsrc1s */
CHECK_FPU_FEATURE(dc, VIS1);
cpu_src1_32 = gen_load_fpr_F(dc, rs1);
gen_store_fpr_F(dc, rd, cpu_src1_32);
break;
case 0x076: /* VIS I fornot2 */
CHECK_FPU_FEATURE(dc, VIS1);
gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_orc_i64);
@ -5442,11 +5453,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
cpu_src1_64 = gen_load_fpr_D(dc, rs2);
gen_store_fpr_D(dc, rd, cpu_src1_64);
break;
case 0x079: /* VIS I fsrc2s */
CHECK_FPU_FEATURE(dc, VIS1);
cpu_src1_32 = gen_load_fpr_F(dc, rs2);
gen_store_fpr_F(dc, rd, cpu_src1_32);
break;
case 0x07a: /* VIS I fornot1 */
CHECK_FPU_FEATURE(dc, VIS1);
gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_orc_i64);