Renesas patches (SH4 and RX)
- Fix few warnings (Thomas Huth) - Fix typos (Lichang Zhao, Chetan Pant) CI jobs results: . https://cirrus-ci.com/build/6368903343374336 . https://gitlab.com/philmd/qemu/-/pipelines/207919103 . https://travis-ci.org/github/philmd/qemu/builds/739133105 -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAl+XW2sACgkQ4+MsLN6t wN5Z+RAAtkD1zbjh3w0zC4kM6npJYpyvIruhQRqpHnHrgTqN6nzmxYquMprRHliI kgiSO6W2nNCqFWnFXBuve82NeWQhhyMZGA4iggCy45a6W/j5t8bfPRdWeFHQjd0O kfakFlB+IFU5lQ2BroRe44IcmGkCMMtuRYK/HCvHZz1a058AOfBpr0egi6cZOXas DEMJNw+FFhcWb6DUaDl0iPKKawzH7GhMkrpVLzWbUd4rrIwzYjDU5w7yp5f1GXG0 63vCO/3vUAmi8cKzTluKBN4pQhzC+lWNCm9MGUVbunHfPWZImfkdnrwJPE95hwuT Dx9WVEsX6P6y3/pN5q7a9J0IdP6BUqIem+yhT4QOWvfoBl/MqqtgwfJh/AcYrrdz LHmQpHyw1aDxWGP4CODdeuTaIA216I6YJosFYb/JHoh2Gw3CUunMsQPZCXz+srQG p+1MZMHPF4A1cElSvX9dtxWxXrHcqZoKOKK6bu9Q6tHSXJ26DMkY35neS7+hBe9B QRdT58DgnR0dBjaF+SGXe/EWqIq0xBNsvwuxZ+gD0sefh+nDyAVnBpYdOERNFY0O 10FWY9yuEYjDAQK0mmjkMbp9xfgQ3YtRCoVAt/YOWBl4nWDlNagX4iSwBvR0i8Xg DtOX7haw3XCQvP2j1pbhbjYXosab/sjxcWo7SrPdNGd7cU74jzY= =dMmS -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/philmd-gitlab/tags/renesas-20201027' into staging Renesas patches (SH4 and RX) - Fix few warnings (Thomas Huth) - Fix typos (Lichang Zhao, Chetan Pant) CI jobs results: . https://cirrus-ci.com/build/6368903343374336 . https://gitlab.com/philmd/qemu/-/pipelines/207919103 . https://travis-ci.org/github/philmd/qemu/builds/739133105 # gpg: Signature made Mon 26 Oct 2020 23:27:39 GMT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * remotes/philmd-gitlab/tags/renesas-20201027: target/rx: Fix Lesser GPL version number target/rx: Fix some comment spelling errors target/sh4: fix some comment spelling errors target/sh4: Update coding style to make checkpatch.pl happy hw/timer/sh_timer: Remove superfluous "break" statements hw/timer/sh_timer: Silence warnings about missing fallthrough statements hw/timer/sh_timer: Coding style clean-up elf: Add EM_RX definition Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
bbc48d2bcb
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@ -117,35 +117,55 @@ static void sh_timer_write(void *opaque, hwaddr offset,
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case 2: freq >>= 6; break;
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case 3: freq >>= 8; break;
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case 4: freq >>= 10; break;
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case 6:
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case 7: if (s->feat & TIMER_FEAT_EXTCLK) break;
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default: hw_error("sh_timer_write: Reserved TPSC value\n"); break;
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case 6:
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case 7:
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if (s->feat & TIMER_FEAT_EXTCLK) {
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break;
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}
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/* fallthrough */
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default:
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hw_error("sh_timer_write: Reserved TPSC value\n");
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}
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switch ((value & TIMER_TCR_CKEG) >> 3) {
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case 0: break;
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case 0:
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break;
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case 1:
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case 2:
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case 3: if (s->feat & TIMER_FEAT_EXTCLK) break;
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default: hw_error("sh_timer_write: Reserved CKEG value\n"); break;
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case 3:
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if (s->feat & TIMER_FEAT_EXTCLK) {
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break;
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}
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/* fallthrough */
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default:
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hw_error("sh_timer_write: Reserved CKEG value\n");
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}
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switch ((value & TIMER_TCR_ICPE) >> 6) {
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case 0: break;
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case 0:
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break;
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case 2:
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case 3: if (s->feat & TIMER_FEAT_CAPT) break;
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default: hw_error("sh_timer_write: Reserved ICPE value\n"); break;
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case 3:
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if (s->feat & TIMER_FEAT_CAPT) {
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break;
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}
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/* fallthrough */
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default:
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hw_error("sh_timer_write: Reserved ICPE value\n");
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}
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if ((value & TIMER_TCR_UNF) == 0)
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if ((value & TIMER_TCR_UNF) == 0) {
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s->int_level = 0;
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}
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value &= ~TIMER_TCR_UNF;
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value &= ~TIMER_TCR_UNF;
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if ((value & TIMER_TCR_ICPF) && (!(s->feat & TIMER_FEAT_CAPT)))
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if ((value & TIMER_TCR_ICPF) && (!(s->feat & TIMER_FEAT_CAPT))) {
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hw_error("sh_timer_write: Reserved ICPF value\n");
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}
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value &= ~TIMER_TCR_ICPF; /* capture not supported */
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value &= ~TIMER_TCR_ICPF; /* capture not supported */
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if (value & TIMER_TCR_RESERVED)
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if (value & TIMER_TCR_RESERVED) {
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hw_error("sh_timer_write: Reserved TCR bits set\n");
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}
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s->tcr = value;
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ptimer_set_limit(s->timer, s->tcor, 0);
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ptimer_set_freq(s->timer, freq);
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@ -158,8 +178,9 @@ static void sh_timer_write(void *opaque, hwaddr offset,
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case OFFSET_TCPR:
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if (s->feat & TIMER_FEAT_CAPT) {
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s->tcpr = value;
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break;
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}
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break;
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}
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/* fallthrough */
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default:
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hw_error("sh_timer_write: Bad offset %x\n", (int)offset);
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}
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@ -241,8 +262,9 @@ static uint64_t tmu012_read(void *opaque, hwaddr offset,
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#endif
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if (offset >= 0x20) {
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if (!(s->feat & TMU012_FEAT_3CHAN))
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hw_error("tmu012_write: Bad channel offset %x\n", (int)offset);
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if (!(s->feat & TMU012_FEAT_3CHAN)) {
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hw_error("tmu012_write: Bad channel offset %x\n", (int)offset);
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}
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return sh_timer_read(s->timer[2], offset - 0x20);
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}
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@ -272,33 +294,36 @@ static void tmu012_write(void *opaque, hwaddr offset,
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#endif
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if (offset >= 0x20) {
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if (!(s->feat & TMU012_FEAT_3CHAN))
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hw_error("tmu012_write: Bad channel offset %x\n", (int)offset);
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if (!(s->feat & TMU012_FEAT_3CHAN)) {
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hw_error("tmu012_write: Bad channel offset %x\n", (int)offset);
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}
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sh_timer_write(s->timer[2], offset - 0x20, value);
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return;
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return;
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}
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if (offset >= 0x14) {
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sh_timer_write(s->timer[1], offset - 0x14, value);
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return;
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return;
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}
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if (offset >= 0x08) {
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sh_timer_write(s->timer[0], offset - 0x08, value);
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return;
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return;
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}
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if (offset == 4) {
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sh_timer_start_stop(s->timer[0], value & (1 << 0));
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sh_timer_start_stop(s->timer[1], value & (1 << 1));
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if (s->feat & TMU012_FEAT_3CHAN)
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if (s->feat & TMU012_FEAT_3CHAN) {
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sh_timer_start_stop(s->timer[2], value & (1 << 2));
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else
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if (value & (1 << 2))
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} else {
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if (value & (1 << 2)) {
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hw_error("tmu012_write: Bad channel\n");
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}
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}
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s->tstr = value;
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return;
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s->tstr = value;
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return;
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}
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if ((s->feat & TMU012_FEAT_TOCR) && offset == 0) {
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@ -314,8 +339,8 @@ static const MemoryRegionOps tmu012_ops = {
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void tmu012_init(MemoryRegion *sysmem, hwaddr base,
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int feat, uint32_t freq,
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qemu_irq ch0_irq, qemu_irq ch1_irq,
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qemu_irq ch2_irq0, qemu_irq ch2_irq1)
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qemu_irq ch0_irq, qemu_irq ch1_irq,
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qemu_irq ch2_irq0, qemu_irq ch2_irq1)
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{
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tmu012_state *s;
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int timer_feat = (feat & TMU012_FEAT_EXTCLK) ? TIMER_FEAT_EXTCLK : 0;
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@ -324,9 +349,10 @@ void tmu012_init(MemoryRegion *sysmem, hwaddr base,
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s->feat = feat;
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s->timer[0] = sh_timer_init(freq, timer_feat, ch0_irq);
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s->timer[1] = sh_timer_init(freq, timer_feat, ch1_irq);
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if (feat & TMU012_FEAT_3CHAN)
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if (feat & TMU012_FEAT_3CHAN) {
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s->timer[2] = sh_timer_init(freq, timer_feat | TIMER_FEAT_CAPT,
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ch2_irq0); /* ch2_irq1 not supported */
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ch2_irq0); /* ch2_irq1 not supported */
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}
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memory_region_init_io(&s->iomem, NULL, &tmu012_ops, s,
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"timer", 0x100000000ULL);
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@ -172,6 +172,8 @@ typedef struct mips_elf_abiflags_v0 {
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#define EM_UNICORE32 110 /* UniCore32 */
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#define EM_RX 173 /* Renesas RX family */
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#define EM_RISCV 243 /* RISC-V */
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#define EM_NANOMIPS 249 /* Wave Computing nanoMIPS */
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@ -7,7 +7,7 @@
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# This library is free software; you can redistribute it and/or
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# modify it under the terms of the GNU Lesser General Public
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# License as published by the Free Software Foundation; either
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# version 2 of the License, or (at your option) any later version.
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# version 2.1 of the License, or (at your option) any later version.
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#
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# This library is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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@ -318,7 +318,7 @@ void helper_swhile(CPURXState *env, uint32_t sz)
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env->psw_c = (tmp <= env->regs[2]);
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}
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/* accumlator operations */
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/* accumulator operations */
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void helper_rmpa(CPURXState *env, uint32_t sz)
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{
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uint64_t result_l, prev;
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@ -1089,7 +1089,7 @@ static void rx_sub(TCGv ret, TCGv arg1, TCGv arg2)
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tcg_gen_xor_i32(temp, arg1, arg2);
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tcg_gen_and_i32(cpu_psw_o, cpu_psw_o, temp);
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tcg_temp_free_i32(temp);
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/* CMP not requred return */
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/* CMP not required return */
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if (ret) {
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tcg_gen_mov_i32(ret, cpu_psw_s);
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}
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@ -160,7 +160,7 @@ typedef struct CPUSH4State {
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uint32_t pteh; /* page table entry high register */
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uint32_t ptel; /* page table entry low register */
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uint32_t ptea; /* page table entry assistance register */
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uint32_t ttb; /* tranlation table base register */
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uint32_t ttb; /* translation table base register */
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uint32_t tea; /* TLB exception address register */
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uint32_t tra; /* TRAPA exception register */
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uint32_t expevt; /* exception event register */
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@ -398,9 +398,11 @@ float32 helper_fsrra_FT(CPUSH4State *env, float32 t0)
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/* "Approximate" 1/sqrt(x) via actual computation. */
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t0 = float32_sqrt(t0, &env->fp_status);
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t0 = float32_div(float32_one, t0, &env->fp_status);
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/* Since this is supposed to be an approximation, an imprecision
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exception is required. One supposes this also follows the usual
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IEEE rule that other exceptions take precidence. */
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/*
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* Since this is supposed to be an approximation, an imprecision
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* exception is required. One supposes this also follows the usual
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* IEEE rule that other exceptions take precedence.
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*/
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if (get_float_exception_flags(&env->fp_status) == 0) {
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set_float_exception_flags(float_flag_inexact, &env->fp_status);
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}
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@ -1959,9 +1959,11 @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env)
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NEXT_INSN;
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switch (ctx->opcode & 0xf00f) {
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case 0x6003: /* mov Rm,Rn */
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/* Here we want to recognize ld_dst being saved for later consumtion,
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or for another input register being copied so that ld_dst need not
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be clobbered during the operation. */
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/*
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* Here we want to recognize ld_dst being saved for later consumption,
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* or for another input register being copied so that ld_dst need not
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* be clobbered during the operation.
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*/
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op_dst = B11_8;
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mv_src = B7_4;
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if (op_dst == ld_dst) {
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