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target/hppa: Fix ADD/SUB trap on overflow for narrow mode

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Fixes: c53e401ed9 ("target/hppa: Remove TARGET_REGISTER_BITS")
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240321184228.611897-2-svens@stackframe.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Sven Schnelle 2024-03-21 19:42:27 +01:00 committed by Richard Henderson
parent 578b8132b2
commit bd1ad92ccf
1 changed files with 6 additions and 0 deletions
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6
target/hppa/translate.c
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@ -1126,6 +1126,9 @@ static void do_add(DisasContext *ctx, unsigned rt, TCGv_i64 in1,
if (is_tsv || cond_need_sv(c)) {
sv = do_add_sv(ctx, dest, in1, in2);
if (is_tsv) {
if (!d) {
tcg_gen_ext32s_i64(sv, sv);
}
/* ??? Need to include overflow from shift. */
gen_helper_tsv(tcg_env, sv);
}
@ -1217,6 +1220,9 @@ static void do_sub(DisasContext *ctx, unsigned rt, TCGv_i64 in1,
if (is_tsv || cond_need_sv(c)) {
sv = do_sub_sv(ctx, dest, in1, in2);
if (is_tsv) {
if (!d) {
tcg_gen_ext32s_i64(sv, sv);
}
gen_helper_tsv(tcg_env, sv);
}
}