target/arm: Mark up sysregs for HFGITR bits 18..47
Mark up the sysreg definitions for the system instructions trapped by HFGITR bits 18..47. These bits cover TLBI TLB maintenance instructions. (If we implemented FEAT_XS we would need to trap some of the instructions added by that feature using these bits; but we don't yet, so will need to add the .fgt markup when we do.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Fuad Tabba <tabba@google.com> Message-id: 20230130182459.3309057-19-peter.maydell@linaro.org Message-id: 20230127175507.2895013-19-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell
parent
132c98cd93
commit
bf2f0625f8
@ -666,6 +666,36 @@ typedef enum FGTBit {
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DO_BIT(HFGITR, ATS1E0W),
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DO_BIT(HFGITR, ATS1E1RP),
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DO_BIT(HFGITR, ATS1E1WP),
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DO_BIT(HFGITR, TLBIVMALLE1OS),
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DO_BIT(HFGITR, TLBIVAE1OS),
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DO_BIT(HFGITR, TLBIASIDE1OS),
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DO_BIT(HFGITR, TLBIVAAE1OS),
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DO_BIT(HFGITR, TLBIVALE1OS),
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DO_BIT(HFGITR, TLBIVAALE1OS),
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DO_BIT(HFGITR, TLBIRVAE1OS),
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DO_BIT(HFGITR, TLBIRVAAE1OS),
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DO_BIT(HFGITR, TLBIRVALE1OS),
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DO_BIT(HFGITR, TLBIRVAALE1OS),
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DO_BIT(HFGITR, TLBIVMALLE1IS),
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DO_BIT(HFGITR, TLBIVAE1IS),
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DO_BIT(HFGITR, TLBIASIDE1IS),
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DO_BIT(HFGITR, TLBIVAAE1IS),
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DO_BIT(HFGITR, TLBIVALE1IS),
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DO_BIT(HFGITR, TLBIVAALE1IS),
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DO_BIT(HFGITR, TLBIRVAE1IS),
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DO_BIT(HFGITR, TLBIRVAAE1IS),
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DO_BIT(HFGITR, TLBIRVALE1IS),
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DO_BIT(HFGITR, TLBIRVAALE1IS),
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DO_BIT(HFGITR, TLBIRVAE1),
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DO_BIT(HFGITR, TLBIRVAAE1),
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DO_BIT(HFGITR, TLBIRVALE1),
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DO_BIT(HFGITR, TLBIRVAALE1),
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DO_BIT(HFGITR, TLBIVMALLE1),
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DO_BIT(HFGITR, TLBIVAE1),
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DO_BIT(HFGITR, TLBIASIDE1),
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DO_BIT(HFGITR, TLBIVAAE1),
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DO_BIT(HFGITR, TLBIVALE1),
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DO_BIT(HFGITR, TLBIVAALE1),
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} FGTBit;
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#undef DO_BIT
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@ -5318,50 +5318,62 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
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{ .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
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.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
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.fgt = FGT_TLBIVMALLE1IS,
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.writefn = tlbi_aa64_vmalle1is_write },
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{ .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
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.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
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.fgt = FGT_TLBIVAE1IS,
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.writefn = tlbi_aa64_vae1is_write },
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{ .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
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.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
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.fgt = FGT_TLBIASIDE1IS,
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.writefn = tlbi_aa64_vmalle1is_write },
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{ .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
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.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
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.fgt = FGT_TLBIVAAE1IS,
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.writefn = tlbi_aa64_vae1is_write },
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{ .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
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.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
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.fgt = FGT_TLBIVALE1IS,
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.writefn = tlbi_aa64_vae1is_write },
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{ .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
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.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
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.fgt = FGT_TLBIVAALE1IS,
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.writefn = tlbi_aa64_vae1is_write },
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{ .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
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.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
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.fgt = FGT_TLBIVMALLE1,
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.writefn = tlbi_aa64_vmalle1_write },
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{ .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
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.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
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.fgt = FGT_TLBIVAE1,
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.writefn = tlbi_aa64_vae1_write },
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{ .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
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.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
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.fgt = FGT_TLBIASIDE1,
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.writefn = tlbi_aa64_vmalle1_write },
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{ .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
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.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
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.fgt = FGT_TLBIVAAE1,
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.writefn = tlbi_aa64_vae1_write },
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{ .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
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.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
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.fgt = FGT_TLBIVALE1,
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.writefn = tlbi_aa64_vae1_write },
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{ .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
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.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
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.fgt = FGT_TLBIVAALE1,
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.writefn = tlbi_aa64_vae1_write },
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{ .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,
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@ -7175,50 +7187,62 @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
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{ .name = "TLBI_RVAE1IS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 1,
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.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
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.fgt = FGT_TLBIRVAE1IS,
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.writefn = tlbi_aa64_rvae1is_write },
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{ .name = "TLBI_RVAAE1IS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 3,
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.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
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.fgt = FGT_TLBIRVAAE1IS,
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.writefn = tlbi_aa64_rvae1is_write },
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{ .name = "TLBI_RVALE1IS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 5,
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.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
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.fgt = FGT_TLBIRVALE1IS,
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.writefn = tlbi_aa64_rvae1is_write },
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{ .name = "TLBI_RVAALE1IS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 7,
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.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
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.fgt = FGT_TLBIRVAALE1IS,
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.writefn = tlbi_aa64_rvae1is_write },
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{ .name = "TLBI_RVAE1OS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1,
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.access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
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.fgt = FGT_TLBIRVAE1OS,
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.writefn = tlbi_aa64_rvae1is_write },
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{ .name = "TLBI_RVAAE1OS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 3,
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.access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
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.fgt = FGT_TLBIRVAAE1OS,
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.writefn = tlbi_aa64_rvae1is_write },
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{ .name = "TLBI_RVALE1OS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 5,
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.access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
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.fgt = FGT_TLBIRVALE1OS,
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.writefn = tlbi_aa64_rvae1is_write },
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{ .name = "TLBI_RVAALE1OS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 7,
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.access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
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.fgt = FGT_TLBIRVAALE1OS,
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.writefn = tlbi_aa64_rvae1is_write },
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{ .name = "TLBI_RVAE1", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1,
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.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
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.fgt = FGT_TLBIRVAE1,
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.writefn = tlbi_aa64_rvae1_write },
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{ .name = "TLBI_RVAAE1", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 3,
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.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
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.fgt = FGT_TLBIRVAAE1,
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.writefn = tlbi_aa64_rvae1_write },
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{ .name = "TLBI_RVALE1", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 5,
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.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
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.fgt = FGT_TLBIRVALE1,
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.writefn = tlbi_aa64_rvae1_write },
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{ .name = "TLBI_RVAALE1", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 7,
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.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
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.fgt = FGT_TLBIRVAALE1,
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.writefn = tlbi_aa64_rvae1_write },
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{ .name = "TLBI_RIPAS2E1IS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 2,
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@ -7290,26 +7314,32 @@ static const ARMCPRegInfo tlbios_reginfo[] = {
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{ .name = "TLBI_VMALLE1OS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 0,
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.access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
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.fgt = FGT_TLBIVMALLE1OS,
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.writefn = tlbi_aa64_vmalle1is_write },
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{ .name = "TLBI_VAE1OS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 1,
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.fgt = FGT_TLBIVAE1OS,
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.access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_vae1is_write },
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{ .name = "TLBI_ASIDE1OS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 2,
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.access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
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.fgt = FGT_TLBIASIDE1OS,
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.writefn = tlbi_aa64_vmalle1is_write },
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{ .name = "TLBI_VAAE1OS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 3,
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.access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
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.fgt = FGT_TLBIVAAE1OS,
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.writefn = tlbi_aa64_vae1is_write },
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{ .name = "TLBI_VALE1OS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 5,
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.access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
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.fgt = FGT_TLBIVALE1OS,
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.writefn = tlbi_aa64_vae1is_write },
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{ .name = "TLBI_VAALE1OS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 7,
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.access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
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.fgt = FGT_TLBIVAALE1OS,
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.writefn = tlbi_aa64_vae1is_write },
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{ .name = "TLBI_ALLE2OS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 0,
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