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target/riscv: Simplify check for EEW = 64 in trans_rvv.c.inc 

Only V extension supports EEW = 64 in these cases: Zve64* extensions don't
support EEW = 64 in these cases as commented before the check.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230215020539.4788-14-liweiwei@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
This commit is contained in:
Weiwei Li 2023-02-15 10:05:38 +08:00 committed by Palmer Dabbelt
parent 6ad831ebf1
commit c1027460dc
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1 changed files with 4 additions and 8 deletions
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12
target/riscv/insn_trans/trans_rvv.c.inc
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@ -1998,8 +1998,7 @@ static bool vmulh_vv_check(DisasContext *s, arg_rmrr *a)
* are not included for EEW=64 in Zve64*. (Section 18.2)
*/
return opivv_check(s, a) &&
(!has_ext(s, RVV) &&
s->cfg_ptr->ext_zve64f ? s->sew != MO_64 : true);
(!has_ext(s, RVV) ? s->sew != MO_64 : true);
}
static bool vmulh_vx_check(DisasContext *s, arg_rmrr *a)
@ -2012,8 +2011,7 @@ static bool vmulh_vx_check(DisasContext *s, arg_rmrr *a)
* are not included for EEW=64 in Zve64*. (Section 18.2)
*/
return opivx_check(s, a) &&
(!has_ext(s, RVV) &&
s->cfg_ptr->ext_zve64f ? s->sew != MO_64 : true);
(!has_ext(s, RVV) ? s->sew != MO_64 : true);
}
GEN_OPIVV_GVEC_TRANS(vmul_vv, mul)
@ -2230,8 +2228,7 @@ static bool vsmul_vv_check(DisasContext *s, arg_rmrr *a)
* for EEW=64 in Zve64*. (Section 18.2)
*/
return opivv_check(s, a) &&
(!has_ext(s, RVV) &&
s->cfg_ptr->ext_zve64f ? s->sew != MO_64 : true);
(!has_ext(s, RVV) ? s->sew != MO_64 : true);
}
static bool vsmul_vx_check(DisasContext *s, arg_rmrr *a)
@ -2242,8 +2239,7 @@ static bool vsmul_vx_check(DisasContext *s, arg_rmrr *a)
* for EEW=64 in Zve64*. (Section 18.2)
*/
return opivx_check(s, a) &&
(!has_ext(s, RVV) &&
s->cfg_ptr->ext_zve64f ? s->sew != MO_64 : true);
(!has_ext(s, RVV) ? s->sew != MO_64 : true);
}
GEN_OPIVV_TRANS(vsmul_vv, vsmul_vv_check)