Hexagon (target/hexagon) Improve code gen for predicated HVX instructions
The following improvements are made for predicated HVX instructions During gen_commit_hvx, unconditionally move the "new" value into the dest Don't set slot_cancelled Remove runtime bookkeeping of which registers were updated Reduce the cases where gen_log_vreg_write[_pair] is called It's only needed for special operands VxxV and VyV Remove gen_log_qreg_write Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-Id: <20230307025828.1612809-15-tsimpson@quicinc.com>
This commit is contained in:
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c2b33d0be9
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@ -136,12 +136,9 @@ For HVX vectors, the generator behaves slightly differently. The wide vectors
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won't fit in a TCGv or TCGv_i64, so we pass TCGv_ptr variables to pass the
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address to helper functions. Here's an example for an HVX vector-add-word
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istruction.
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static void generate_V6_vaddw(
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CPUHexagonState *env,
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DisasContext *ctx,
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Insn *insn,
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Packet *pkt)
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static void generate_V6_vaddw(DisasContext *ctx)
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{
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Insn *insn __attribute__((unused)) = ctx->insn;
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const int VdN = insn->regno[0];
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const intptr_t VdV_off =
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ctx_future_vreg_off(ctx, VdN, 1, true);
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@ -157,9 +154,7 @@ istruction.
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TCGv_ptr VvV = tcg_temp_new_ptr();
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tcg_gen_addi_ptr(VuV, cpu_env, VuV_off);
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tcg_gen_addi_ptr(VvV, cpu_env, VvV_off);
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TCGv slot = tcg_constant_tl(insn->slot);
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gen_helper_V6_vaddw(cpu_env, VdV, VuV, VvV, slot);
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gen_log_vreg_write(ctx, VdV_off, VdN, EXT_DFL, insn->slot, false);
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gen_helper_V6_vaddw(cpu_env, VdV, VuV, VvV);
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}
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Notice that we also generate a variable named <operand>_off for each operand of
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@ -172,12 +167,9 @@ functions from tcg-op-gvec.h. Here's the override for this instruction.
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Finally, we notice that the override doesn't use the TCGv_ptr variables, so
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we don't generate them when an override is present. Here is what we generate
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when the override is present.
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static void generate_V6_vaddw(
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CPUHexagonState *env,
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DisasContext *ctx,
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Insn *insn,
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Packet *pkt)
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static void generate_V6_vaddw(DisasContext *ctx)
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{
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Insn *insn __attribute__((unused)) = ctx->insn;
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const int VdN = insn->regno[0];
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const intptr_t VdV_off =
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ctx_future_vreg_off(ctx, VdN, 1, true);
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@ -188,7 +180,6 @@ when the override is present.
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const intptr_t VvV_off =
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vreg_src_off(ctx, VvN);
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fGEN_TCG_V6_vaddw({ fHIDE(int i;) fVFOREACH(32, i) { VdV.w[i] = VuV.w[i] + VvV.w[i] ; } });
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gen_log_vreg_write(ctx, VdV_off, VdN, EXT_DFL, insn->slot, false);
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}
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We also generate an analyze_<tag> function for each instruction. Currently,
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@ -281,10 +272,8 @@ For Hexagon Vector eXtensions (HVX), the following fields are used
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VRegs Vector registers
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future_VRegs Registers to be stored during packet commit
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tmp_VRegs Temporary registers *not* stored during commit
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VRegs_updated Mask of predicated vector writes
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QRegs Q (vector predicate) registers
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future_QRegs Registers to be stored during packet commit
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QRegs_updated Mask of predicated vector writes
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*** Debugging ***
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@ -1,5 +1,5 @@
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/*
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* Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights Reserved.
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* Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -111,11 +111,8 @@ typedef struct CPUArchState {
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MMVector future_VRegs[VECTOR_TEMPS_MAX] QEMU_ALIGNED(16);
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MMVector tmp_VRegs[VECTOR_TEMPS_MAX] QEMU_ALIGNED(16);
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VRegMask VRegs_updated;
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MMQReg QRegs[NUM_QREGS] QEMU_ALIGNED(16);
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MMQReg future_QRegs[NUM_QREGS] QEMU_ALIGNED(16);
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QRegMask QRegs_updated;
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/* Temporaries used within instructions */
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MMVectorPair VuuV QEMU_ALIGNED(16);
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@ -110,8 +110,7 @@ def analyze_opn_old(f, tag, regtype, regid, regno):
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if (regid in {"d", "e", "x"}):
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f.write(" const int %s = insn->regno[%d];\n" % \
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(regN, regno))
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f.write(" ctx_log_qreg_write(ctx, %s, %s);\n" % \
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(regN, predicated))
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f.write(" ctx_log_qreg_write(ctx, %s);\n" % (regN))
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elif (regid in {"s", "t", "u", "v"}):
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f.write("// const int %s = insn->regno[%d];\n" % \
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(regN, regno))
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@ -176,8 +176,7 @@ def genptr_decl(f, tag, regtype, regid, regno):
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(regtype, regid, regno))
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f.write(" const intptr_t %s%sV_off =\n" % \
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(regtype, regid))
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f.write(" offsetof(CPUHexagonState,\n")
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f.write(" future_QRegs[%s%sN]);\n" % \
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f.write(" get_result_qreg(ctx, %s%sN);\n" % \
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(regtype, regid))
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if (not hex_common.skip_qemu_helper(tag)):
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f.write(" TCGv_ptr %s%sV = tcg_temp_new_ptr();\n" % \
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@ -406,36 +405,18 @@ def genptr_dst_write(f, tag, regtype, regid):
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def genptr_dst_write_ext(f, tag, regtype, regid, newv="EXT_DFL"):
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if (regtype == "V"):
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if (regid in {"dd", "xx", "yy"}):
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if ('A_CONDEXEC' in hex_common.attribdict[tag]):
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is_predicated = "true"
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else:
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is_predicated = "false"
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if (regid in {"xx"}):
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f.write(" gen_log_vreg_write_pair(ctx, %s%sV_off, %s%sN, " % \
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(regtype, regid, regtype, regid))
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f.write("%s, insn->slot, %s);\n" % \
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(newv, is_predicated))
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elif (regid in {"d", "x", "y"}):
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if ('A_CONDEXEC' in hex_common.attribdict[tag]):
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is_predicated = "true"
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else:
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is_predicated = "false"
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f.write(" gen_log_vreg_write(ctx, %s%sV_off, %s%sN, %s, " % \
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f.write("%s);\n" % \
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(newv))
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elif (regid in {"y"}):
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f.write(" gen_log_vreg_write(ctx, %s%sV_off, %s%sN, %s);\n" % \
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(regtype, regid, regtype, regid, newv))
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f.write("insn->slot, %s);\n" % \
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(is_predicated))
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else:
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elif (regid not in {"dd", "d", "x"}):
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print("Bad register parse: ", regtype, regid)
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elif (regtype == "Q"):
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if (regid in {"d", "e", "x"}):
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if ('A_CONDEXEC' in hex_common.attribdict[tag]):
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is_predicated = "true"
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else:
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is_predicated = "false"
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f.write(" gen_log_qreg_write(%s%sV_off, %s%sN, %s, " % \
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(regtype, regid, regtype, regid, newv))
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f.write("insn->slot, %s);\n" % (is_predicated))
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else:
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if (regid not in {"d", "e", "x"}):
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print("Bad register parse: ", regtype, regid)
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else:
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print("Bad register parse: ", regtype, regid)
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@ -1,5 +1,5 @@
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/*
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* Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights Reserved.
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* Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -133,16 +133,11 @@ static inline void assert_vhist_tmp(DisasContext *ctx)
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do { \
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TCGv lsb = tcg_temp_new(); \
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TCGLabel *false_label = gen_new_label(); \
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TCGLabel *end_label = gen_new_label(); \
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tcg_gen_andi_tl(lsb, PsV, 1); \
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tcg_gen_brcondi_tl(TCG_COND_NE, lsb, PRED, false_label); \
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tcg_gen_gvec_mov(MO_64, VdV_off, VuV_off, \
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sizeof(MMVector), sizeof(MMVector)); \
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tcg_gen_br(end_label); \
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gen_set_label(false_label); \
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tcg_gen_ori_tl(hex_slot_cancelled, hex_slot_cancelled, \
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1 << insn->slot); \
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gen_set_label(end_label); \
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} while (0)
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@ -547,17 +542,12 @@ static inline void assert_vhist_tmp(DisasContext *ctx)
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do { \
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TCGv LSB = tcg_temp_new(); \
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TCGLabel *false_label = gen_new_label(); \
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TCGLabel *end_label = gen_new_label(); \
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GET_EA; \
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PRED; \
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tcg_gen_brcondi_tl(TCG_COND_EQ, LSB, 0, false_label); \
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gen_vreg_load(ctx, DSTOFF, EA, true); \
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INC; \
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tcg_gen_br(end_label); \
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gen_set_label(false_label); \
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tcg_gen_ori_tl(hex_slot_cancelled, hex_slot_cancelled, \
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1 << insn->slot); \
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gen_set_label(end_label); \
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} while (0)
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#define fGEN_TCG_PRED_VEC_LOAD_pred_pi \
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@ -717,17 +707,12 @@ static inline void assert_vhist_tmp(DisasContext *ctx)
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do { \
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TCGv LSB = tcg_temp_new(); \
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TCGLabel *false_label = gen_new_label(); \
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TCGLabel *end_label = gen_new_label(); \
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GET_EA; \
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PRED; \
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tcg_gen_brcondi_tl(TCG_COND_EQ, LSB, 0, false_label); \
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gen_vreg_store(ctx, EA, SRCOFF, insn->slot, ALIGN); \
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INC; \
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tcg_gen_br(end_label); \
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gen_set_label(false_label); \
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tcg_gen_ori_tl(hex_slot_cancelled, hex_slot_cancelled, \
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1 << insn->slot); \
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gen_set_label(end_label); \
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} while (0)
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#define fGEN_TCG_PRED_VEC_STORE_pred_pi(ALIGN) \
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@ -985,68 +985,32 @@ static intptr_t vreg_src_off(DisasContext *ctx, int num)
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}
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static void gen_log_vreg_write(DisasContext *ctx, intptr_t srcoff, int num,
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VRegWriteType type, int slot_num,
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bool is_predicated)
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VRegWriteType type)
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{
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TCGLabel *label_end = NULL;
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intptr_t dstoff;
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if (is_predicated) {
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TCGv cancelled = tcg_temp_new();
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label_end = gen_new_label();
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/* Don't do anything if the slot was cancelled */
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tcg_gen_extract_tl(cancelled, hex_slot_cancelled, slot_num, 1);
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tcg_gen_brcondi_tl(TCG_COND_NE, cancelled, 0, label_end);
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}
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if (type != EXT_TMP) {
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dstoff = ctx_future_vreg_off(ctx, num, 1, true);
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tcg_gen_gvec_mov(MO_64, dstoff, srcoff,
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sizeof(MMVector), sizeof(MMVector));
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tcg_gen_ori_tl(hex_VRegs_updated, hex_VRegs_updated, 1 << num);
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} else {
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dstoff = ctx_tmp_vreg_off(ctx, num, 1, false);
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tcg_gen_gvec_mov(MO_64, dstoff, srcoff,
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sizeof(MMVector), sizeof(MMVector));
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}
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if (is_predicated) {
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gen_set_label(label_end);
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}
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}
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static void gen_log_vreg_write_pair(DisasContext *ctx, intptr_t srcoff, int num,
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VRegWriteType type, int slot_num,
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bool is_predicated)
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VRegWriteType type)
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{
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gen_log_vreg_write(ctx, srcoff, num ^ 0, type, slot_num, is_predicated);
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gen_log_vreg_write(ctx, srcoff, num ^ 0, type);
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srcoff += sizeof(MMVector);
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gen_log_vreg_write(ctx, srcoff, num ^ 1, type, slot_num, is_predicated);
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gen_log_vreg_write(ctx, srcoff, num ^ 1, type);
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}
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static void gen_log_qreg_write(intptr_t srcoff, int num, int vnew,
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int slot_num, bool is_predicated)
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static intptr_t get_result_qreg(DisasContext *ctx, int qnum)
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{
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TCGLabel *label_end = NULL;
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intptr_t dstoff;
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if (is_predicated) {
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TCGv cancelled = tcg_temp_new();
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label_end = gen_new_label();
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/* Don't do anything if the slot was cancelled */
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tcg_gen_extract_tl(cancelled, hex_slot_cancelled, slot_num, 1);
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tcg_gen_brcondi_tl(TCG_COND_NE, cancelled, 0, label_end);
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}
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dstoff = offsetof(CPUHexagonState, future_QRegs[num]);
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tcg_gen_gvec_mov(MO_64, dstoff, srcoff, sizeof(MMQReg), sizeof(MMQReg));
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if (is_predicated) {
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tcg_gen_ori_tl(hex_QRegs_updated, hex_QRegs_updated, 1 << num);
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gen_set_label(label_end);
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}
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return offsetof(CPUHexagonState, future_QRegs[qnum]);
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}
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static void gen_vreg_load(DisasContext *ctx, intptr_t dstoff, TCGv src,
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@ -56,8 +56,6 @@ TCGv hex_dczero_addr;
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TCGv hex_llsc_addr;
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TCGv hex_llsc_val;
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TCGv_i64 hex_llsc_val_i64;
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TCGv hex_VRegs_updated;
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TCGv hex_QRegs_updated;
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TCGv hex_vstore_addr[VSTORES_MAX];
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TCGv hex_vstore_size[VSTORES_MAX];
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TCGv hex_vstore_pending[VSTORES_MAX];
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@ -248,12 +246,11 @@ static bool check_for_attrib(Packet *pkt, int attrib)
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static bool need_slot_cancelled(Packet *pkt)
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{
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/* We only need slot_cancelled for conditional store and HVX instructions */
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/* We only need slot_cancelled for conditional store instructions */
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for (int i = 0; i < pkt->num_insns; i++) {
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uint16_t opcode = pkt->insn[i].opcode;
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if (GET_ATTRIB(opcode, A_CONDEXEC) &&
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(GET_ATTRIB(opcode, A_STORE) ||
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GET_ATTRIB(opcode, A_CVI))) {
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GET_ATTRIB(opcode, A_SCALAR_STORE)) {
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return true;
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}
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}
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@ -453,11 +450,6 @@ static void gen_start_packet(DisasContext *ctx)
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i = find_next_bit(ctx->predicated_tmp_vregs, NUM_VREGS, i + 1);
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}
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}
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if (pkt->pkt_has_hvx) {
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tcg_gen_movi_tl(hex_VRegs_updated, 0);
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tcg_gen_movi_tl(hex_QRegs_updated, 0);
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}
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}
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bool is_gather_store_insn(DisasContext *ctx)
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@ -725,65 +717,31 @@ static void gen_commit_hvx(DisasContext *ctx)
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/*
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* for (i = 0; i < ctx->vreg_log_idx; i++) {
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* int rnum = ctx->vreg_log[i];
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* if (ctx->vreg_is_predicated[i]) {
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* if (env->VRegs_updated & (1 << rnum)) {
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* env->VRegs[rnum] = env->future_VRegs[rnum];
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* }
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* } else {
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* env->VRegs[rnum] = env->future_VRegs[rnum];
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* }
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* }
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*/
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for (i = 0; i < ctx->vreg_log_idx; i++) {
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int rnum = ctx->vreg_log[i];
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bool is_predicated = ctx->vreg_is_predicated[i];
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intptr_t dstoff = offsetof(CPUHexagonState, VRegs[rnum]);
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intptr_t srcoff = ctx_future_vreg_off(ctx, rnum, 1, false);
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size_t size = sizeof(MMVector);
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if (is_predicated) {
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TCGv cmp = tcg_temp_new();
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TCGLabel *label_skip = gen_new_label();
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tcg_gen_andi_tl(cmp, hex_VRegs_updated, 1 << rnum);
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tcg_gen_brcondi_tl(TCG_COND_EQ, cmp, 0, label_skip);
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tcg_gen_gvec_mov(MO_64, dstoff, srcoff, size, size);
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gen_set_label(label_skip);
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} else {
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tcg_gen_gvec_mov(MO_64, dstoff, srcoff, size, size);
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}
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}
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/*
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* for (i = 0; i < ctx->qreg_log_idx; i++) {
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* int rnum = ctx->qreg_log[i];
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* if (ctx->qreg_is_predicated[i]) {
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* if (env->QRegs_updated) & (1 << rnum)) {
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* env->QRegs[rnum] = env->future_QRegs[rnum];
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* }
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* } else {
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* env->QRegs[rnum] = env->future_QRegs[rnum];
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* }
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* }
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*/
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for (i = 0; i < ctx->qreg_log_idx; i++) {
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int rnum = ctx->qreg_log[i];
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bool is_predicated = ctx->qreg_is_predicated[i];
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intptr_t dstoff = offsetof(CPUHexagonState, QRegs[rnum]);
|
||||
intptr_t srcoff = offsetof(CPUHexagonState, future_QRegs[rnum]);
|
||||
size_t size = sizeof(MMQReg);
|
||||
|
||||
if (is_predicated) {
|
||||
TCGv cmp = tcg_temp_new();
|
||||
TCGLabel *label_skip = gen_new_label();
|
||||
|
||||
tcg_gen_andi_tl(cmp, hex_QRegs_updated, 1 << rnum);
|
||||
tcg_gen_brcondi_tl(TCG_COND_EQ, cmp, 0, label_skip);
|
||||
tcg_gen_gvec_mov(MO_64, dstoff, srcoff, size, size);
|
||||
gen_set_label(label_skip);
|
||||
} else {
|
||||
tcg_gen_gvec_mov(MO_64, dstoff, srcoff, size, size);
|
||||
}
|
||||
}
|
||||
|
||||
if (pkt_has_hvx_store(ctx->pkt)) {
|
||||
|
@ -1129,10 +1087,6 @@ void hexagon_translate_init(void)
|
|||
offsetof(CPUHexagonState, llsc_val), "llsc_val");
|
||||
hex_llsc_val_i64 = tcg_global_mem_new_i64(cpu_env,
|
||||
offsetof(CPUHexagonState, llsc_val_i64), "llsc_val_i64");
|
||||
hex_VRegs_updated = tcg_global_mem_new(cpu_env,
|
||||
offsetof(CPUHexagonState, VRegs_updated), "VRegs_updated");
|
||||
hex_QRegs_updated = tcg_global_mem_new(cpu_env,
|
||||
offsetof(CPUHexagonState, QRegs_updated), "QRegs_updated");
|
||||
for (i = 0; i < STORES_MAX; i++) {
|
||||
snprintf(store_addr_names[i], NAME_LEN, "store_addr_%d", i);
|
||||
hex_store_addr[i] = tcg_global_mem_new(cpu_env,
|
||||
|
|
|
@ -49,7 +49,6 @@ typedef struct DisasContext {
|
|||
int tmp_vregs_idx;
|
||||
int tmp_vregs_num[VECTOR_TEMPS_MAX];
|
||||
int vreg_log[NUM_VREGS];
|
||||
bool vreg_is_predicated[NUM_VREGS];
|
||||
int vreg_log_idx;
|
||||
DECLARE_BITMAP(vregs_updated_tmp, NUM_VREGS);
|
||||
DECLARE_BITMAP(vregs_updated, NUM_VREGS);
|
||||
|
@ -57,7 +56,6 @@ typedef struct DisasContext {
|
|||
DECLARE_BITMAP(predicated_future_vregs, NUM_VREGS);
|
||||
DECLARE_BITMAP(predicated_tmp_vregs, NUM_VREGS);
|
||||
int qreg_log[NUM_QREGS];
|
||||
bool qreg_is_predicated[NUM_QREGS];
|
||||
int qreg_log_idx;
|
||||
bool pre_commit;
|
||||
TCGCond branch_cond;
|
||||
|
@ -111,9 +109,11 @@ static inline void ctx_log_vreg_write(DisasContext *ctx,
|
|||
bool is_predicated)
|
||||
{
|
||||
if (type != EXT_TMP) {
|
||||
if (!test_bit(rnum, ctx->vregs_updated)) {
|
||||
ctx->vreg_log[ctx->vreg_log_idx] = rnum;
|
||||
ctx->vreg_is_predicated[ctx->vreg_log_idx] = is_predicated;
|
||||
ctx->vreg_log_idx++;
|
||||
set_bit(rnum, ctx->vregs_updated);
|
||||
}
|
||||
|
||||
set_bit(rnum, ctx->vregs_updated);
|
||||
if (is_predicated) {
|
||||
|
@ -140,10 +140,9 @@ static inline void ctx_log_vreg_write_pair(DisasContext *ctx,
|
|||
}
|
||||
|
||||
static inline void ctx_log_qreg_write(DisasContext *ctx,
|
||||
int rnum, bool is_predicated)
|
||||
int rnum)
|
||||
{
|
||||
ctx->qreg_log[ctx->qreg_log_idx] = rnum;
|
||||
ctx->qreg_is_predicated[ctx->qreg_log_idx] = is_predicated;
|
||||
ctx->qreg_log_idx++;
|
||||
}
|
||||
|
||||
|
@ -164,8 +163,6 @@ extern TCGv hex_dczero_addr;
|
|||
extern TCGv hex_llsc_addr;
|
||||
extern TCGv hex_llsc_val;
|
||||
extern TCGv_i64 hex_llsc_val_i64;
|
||||
extern TCGv hex_VRegs_updated;
|
||||
extern TCGv hex_QRegs_updated;
|
||||
extern TCGv hex_vstore_addr[VSTORES_MAX];
|
||||
extern TCGv hex_vstore_size[VSTORES_MAX];
|
||||
extern TCGv hex_vstore_pending[VSTORES_MAX];
|
||||
|
|
Loading…
Reference in New Issue