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target-arm queue: 

* add missing condexec updates when emulating architectural breakpoints
    and coprocessor access checks in Thumb translation (could in theory
    cause problems when these happened inside a Thumb IT block and an
    exception was taken)
  * arm_gic: correctly restore nested IRQ priority
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Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20151119' into staging

target-arm queue:
 * add missing condexec updates when emulating architectural breakpoints
   and coprocessor access checks in Thumb translation (could in theory
   cause problems when these happened inside a Thumb IT block and an
   exception was taken)
 * arm_gic: correctly restore nested IRQ priority

# gpg: Signature made Thu 19 Nov 2015 13:29:37 GMT using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>"
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"

* remotes/pmaydell/tags/pull-target-arm-20151119:
  target-arm: Update condexec before arch BP check in AA32 translation
  target-arm: Update condexec before CP access check in AA32 translation
  hw/arm_gic: Correctly restore nested irq priority

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2015-11-19 15:56:50 +00:00
parent 80fda8f609 ce8a1b5449
commit c601a244a4
2 changed files with 4 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
hw/intc/arm_gic.c
View File

@ -254,9 +254,9 @@ static void gic_activate_irq(GICState *s, int cpu, int irq)
int bitno = preemption_level % 32;
if (gic_has_groups(s) && GIC_TEST_GROUP(irq, (1 << cpu))) {
s->nsapr[regno][cpu] &= (1 << bitno);
s->nsapr[regno][cpu] |= (1 << bitno);
} else {
s->apr[regno][cpu] &= (1 << bitno);
s->apr[regno][cpu] |= (1 << bitno);
}
s->running_priority[cpu] = prio;

2
target-arm/translate.c
View File

@ -7210,6 +7210,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn)
break;
}
gen_set_condexec(s);
gen_set_pc_im(s, s->pc - 4);
tmpptr = tcg_const_ptr(ri);
tcg_syn = tcg_const_i32(syndrome);
@ -11373,6 +11374,7 @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
if (bp->pc == dc->pc) {
if (bp->flags & BP_CPU) {
gen_set_condexec(dc);
gen_set_pc_im(dc, dc->pc);
gen_helper_check_breakpoints(cpu_env);
/* End the TB early; it's likely not going to be executed */