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LoongArch updates: 

Store value in SET_FPU_* macros.
   Fix unused variable Werrors in acpi-build.c
   Update xml to match upstream gdb.
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Merge tag 'pull-la-20220805' of https://gitlab.com/rth7680/qemu into staging

LoongArch updates:
  Store value in SET_FPU_* macros.
  Fix unused variable Werrors in acpi-build.c
  Update xml to match upstream gdb.

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# gpg: Signature made Fri 05 Aug 2022 12:53:30 PM PDT
# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate]

* tag 'pull-la-20220805' of https://gitlab.com/rth7680/qemu:
  target/loongarch: Update gdb_set_fpu() and gdb_get_fpu()
  target/loongarch: Update loongarch-fpu.xml
  target/loongarch: update loongarch-base64.xml
  target/loongarch: add gdb_arch_name()
  target/loongarch: Fix GDB get the wrong pc
  hw/loongarch: remove acpi-build.c unused variable 'aml_len'
  target/loongarch: Fix macros SET_FPU_* in cpu.h

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2022-08-05 12:55:53 -07:00
parent e0d8bb9800 2f149c759f
commit c669f22f1a
10 changed files with 119 additions and 110 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
configs/targets/loongarch64-softmmu.mak
View File

@ -1,5 +1,5 @@
TARGET_ARCH=loongarch64
TARGET_BASE_ARCH=loongarch
TARGET_SUPPORTS_MTTCG=y
TARGET_XML_FILES= gdb-xml/loongarch-base64.xml gdb-xml/loongarch-fpu64.xml
TARGET_XML_FILES= gdb-xml/loongarch-base64.xml gdb-xml/loongarch-fpu.xml
TARGET_NEED_FDT=y

13
gdb-xml/loongarch-base64.xml
View File

@ -1,5 +1,5 @@
<?xml version="1.0"?>
<!-- Copyright (C) 2021 Free Software Foundation, Inc.
<!-- Copyright (C) 2022 Free Software Foundation, Inc.
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
@ -8,9 +8,9 @@
<!DOCTYPE feature SYSTEM "gdb-target.dtd">
<feature name="org.gnu.gdb.loongarch.base">
<reg name="r0" bitsize="64" type="uint64" group="general"/>
<reg name="r1" bitsize="64" type="uint64" group="general"/>
<reg name="r2" bitsize="64" type="uint64" group="general"/>
<reg name="r3" bitsize="64" type="uint64" group="general"/>
<reg name="r1" bitsize="64" type="code_ptr" group="general"/>
<reg name="r2" bitsize="64" type="data_ptr" group="general"/>
<reg name="r3" bitsize="64" type="data_ptr" group="general"/>
<reg name="r4" bitsize="64" type="uint64" group="general"/>
<reg name="r5" bitsize="64" type="uint64" group="general"/>
<reg name="r6" bitsize="64" type="uint64" group="general"/>
@ -29,7 +29,7 @@
<reg name="r19" bitsize="64" type="uint64" group="general"/>
<reg name="r20" bitsize="64" type="uint64" group="general"/>
<reg name="r21" bitsize="64" type="uint64" group="general"/>
<reg name="r22" bitsize="64" type="uint64" group="general"/>
<reg name="r22" bitsize="64" type="data_ptr" group="general"/>
<reg name="r23" bitsize="64" type="uint64" group="general"/>
<reg name="r24" bitsize="64" type="uint64" group="general"/>
<reg name="r25" bitsize="64" type="uint64" group="general"/>
@ -39,6 +39,7 @@
<reg name="r29" bitsize="64" type="uint64" group="general"/>
<reg name="r30" bitsize="64" type="uint64" group="general"/>
<reg name="r31" bitsize="64" type="uint64" group="general"/>
<reg name="orig_a0" bitsize="64" type="uint64" group="general"/>
<reg name="pc" bitsize="64" type="code_ptr" group="general"/>
<reg name="badvaddr" bitsize="64" type="code_ptr" group="general"/>
<reg name="badv" bitsize="64" type="code_ptr" group="general"/>
</feature>

50
gdb-xml/loongarch-fpu.xml Normal file
View File

@ -0,0 +1,50 @@
<?xml version="1.0"?>
<!-- Copyright (C) 2021 Free Software Foundation, Inc.
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved. -->
<!DOCTYPE feature SYSTEM "gdb-target.dtd">
<feature name="org.gnu.gdb.loongarch.fpu">
<union id="fputype">
<field name="f" type="ieee_single"/>
<field name="d" type="ieee_double"/>
</union>
<reg name="f0" bitsize="64" type="fputype" group="float"/>
<reg name="f1" bitsize="64" type="fputype" group="float"/>
<reg name="f2" bitsize="64" type="fputype" group="float"/>
<reg name="f3" bitsize="64" type="fputype" group="float"/>
<reg name="f4" bitsize="64" type="fputype" group="float"/>
<reg name="f5" bitsize="64" type="fputype" group="float"/>
<reg name="f6" bitsize="64" type="fputype" group="float"/>
<reg name="f7" bitsize="64" type="fputype" group="float"/>
<reg name="f8" bitsize="64" type="fputype" group="float"/>
<reg name="f9" bitsize="64" type="fputype" group="float"/>
<reg name="f10" bitsize="64" type="fputype" group="float"/>
<reg name="f11" bitsize="64" type="fputype" group="float"/>
<reg name="f12" bitsize="64" type="fputype" group="float"/>
<reg name="f13" bitsize="64" type="fputype" group="float"/>
<reg name="f14" bitsize="64" type="fputype" group="float"/>
<reg name="f15" bitsize="64" type="fputype" group="float"/>
<reg name="f16" bitsize="64" type="fputype" group="float"/>
<reg name="f17" bitsize="64" type="fputype" group="float"/>
<reg name="f18" bitsize="64" type="fputype" group="float"/>
<reg name="f19" bitsize="64" type="fputype" group="float"/>
<reg name="f20" bitsize="64" type="fputype" group="float"/>
<reg name="f21" bitsize="64" type="fputype" group="float"/>
<reg name="f22" bitsize="64" type="fputype" group="float"/>
<reg name="f23" bitsize="64" type="fputype" group="float"/>
<reg name="f24" bitsize="64" type="fputype" group="float"/>
<reg name="f25" bitsize="64" type="fputype" group="float"/>
<reg name="f26" bitsize="64" type="fputype" group="float"/>
<reg name="f27" bitsize="64" type="fputype" group="float"/>
<reg name="f28" bitsize="64" type="fputype" group="float"/>
<reg name="f29" bitsize="64" type="fputype" group="float"/>
<reg name="f30" bitsize="64" type="fputype" group="float"/>
<reg name="f31" bitsize="64" type="fputype" group="float"/>
<reg name="fcc" bitsize="64" type="uint64" group="float"/>
<reg name="fcsr" bitsize="32" type="uint32" group="float"/>
</feature>

57
gdb-xml/loongarch-fpu64.xml
View File

@ -1,57 +0,0 @@
<?xml version="1.0"?>
<!-- Copyright (C) 2021 Free Software Foundation, Inc.
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved. -->
<!DOCTYPE feature SYSTEM "gdb-target.dtd">
<feature name="org.gnu.gdb.loongarch.fpu">
<union id="fpu64type">
<field name="f" type="ieee_single"/>
<field name="d" type="ieee_double"/>
</union>
<reg name="f0" bitsize="64" type="fpu64type" group="float"/>
<reg name="f1" bitsize="64" type="fpu64type" group="float"/>
<reg name="f2" bitsize="64" type="fpu64type" group="float"/>
<reg name="f3" bitsize="64" type="fpu64type" group="float"/>
<reg name="f4" bitsize="64" type="fpu64type" group="float"/>
<reg name="f5" bitsize="64" type="fpu64type" group="float"/>
<reg name="f6" bitsize="64" type="fpu64type" group="float"/>
<reg name="f7" bitsize="64" type="fpu64type" group="float"/>
<reg name="f8" bitsize="64" type="fpu64type" group="float"/>
<reg name="f9" bitsize="64" type="fpu64type" group="float"/>
<reg name="f10" bitsize="64" type="fpu64type" group="float"/>
<reg name="f11" bitsize="64" type="fpu64type" group="float"/>
<reg name="f12" bitsize="64" type="fpu64type" group="float"/>
<reg name="f13" bitsize="64" type="fpu64type" group="float"/>
<reg name="f14" bitsize="64" type="fpu64type" group="float"/>
<reg name="f15" bitsize="64" type="fpu64type" group="float"/>
<reg name="f16" bitsize="64" type="fpu64type" group="float"/>
<reg name="f17" bitsize="64" type="fpu64type" group="float"/>
<reg name="f18" bitsize="64" type="fpu64type" group="float"/>
<reg name="f19" bitsize="64" type="fpu64type" group="float"/>
<reg name="f20" bitsize="64" type="fpu64type" group="float"/>
<reg name="f21" bitsize="64" type="fpu64type" group="float"/>
<reg name="f22" bitsize="64" type="fpu64type" group="float"/>
<reg name="f23" bitsize="64" type="fpu64type" group="float"/>
<reg name="f24" bitsize="64" type="fpu64type" group="float"/>
<reg name="f25" bitsize="64" type="fpu64type" group="float"/>
<reg name="f26" bitsize="64" type="fpu64type" group="float"/>
<reg name="f27" bitsize="64" type="fpu64type" group="float"/>
<reg name="f28" bitsize="64" type="fpu64type" group="float"/>
<reg name="f29" bitsize="64" type="fpu64type" group="float"/>
<reg name="f30" bitsize="64" type="fpu64type" group="float"/>
<reg name="f31" bitsize="64" type="fpu64type" group="float"/>
<reg name="fcc0" bitsize="8" type="uint8" group="float"/>
<reg name="fcc1" bitsize="8" type="uint8" group="float"/>
<reg name="fcc2" bitsize="8" type="uint8" group="float"/>
<reg name="fcc3" bitsize="8" type="uint8" group="float"/>
<reg name="fcc4" bitsize="8" type="uint8" group="float"/>
<reg name="fcc5" bitsize="8" type="uint8" group="float"/>
<reg name="fcc6" bitsize="8" type="uint8" group="float"/>
<reg name="fcc7" bitsize="8" type="uint8" group="float"/>
<reg name="fcsr" bitsize="32" type="uint32" group="float"/>
</feature>

11
hw/loongarch/acpi-build.c
View File

@ -411,9 +411,8 @@ static void acpi_build(AcpiBuildTables *tables, MachineState *machine)
LoongArchMachineState *lams = LOONGARCH_MACHINE(machine);
GArray *table_offsets;
AcpiFadtData fadt_data;
unsigned facs, rsdt, fadt, dsdt;
unsigned facs, rsdt, dsdt;
uint8_t *u;
size_t aml_len = 0;
GArray *tables_blob = tables->table_data;
init_common_fadt_data(&fadt_data);
@ -437,21 +436,13 @@ static void acpi_build(AcpiBuildTables *tables, MachineState *machine)
dsdt = tables_blob->len;
build_dsdt(tables_blob, tables->linker, machine);
/*
* Count the size of the DSDT, we will need it for
* legacy sizing of ACPI tables.
*/
aml_len += tables_blob->len - dsdt;
/* ACPI tables pointed to by RSDT */
fadt = tables_blob->len;
acpi_add_table(table_offsets, tables_blob);
fadt_data.facs_tbl_offset = &facs;
fadt_data.dsdt_tbl_offset = &dsdt;
fadt_data.xdsdt_tbl_offset = &dsdt;
build_fadt(tables_blob, tables->linker, &fadt_data,
lams->oem_id, lams->oem_table_id);
aml_len += tables_blob->len - fadt;
acpi_add_table(table_offsets, tables_blob);
build_madt(tables_blob, tables->linker, lams);

24
linux-user/loongarch64/signal.c
View File

@ -71,26 +71,6 @@ struct extctx_layout {
struct ctx_layout end;
};
/* The kernel's sc_save_fcc macro is a sequence of MOVCF2GR+BSTRINS. */
static uint64_t read_all_fcc(CPULoongArchState *env)
{
uint64_t ret = 0;
for (int i = 0; i < 8; ++i) {
ret |= (uint64_t)env->cf[i] << (i * 8);
}
return ret;
}
/* The kernel's sc_restore_fcc macro is a sequence of BSTRPICK+MOVGR2CF. */
static void write_all_fcc(CPULoongArchState *env, uint64_t val)
{
for (int i = 0; i < 8; ++i) {
env->cf[i] = (val >> (i * 8)) & 1;
}
}
static abi_ptr extframe_alloc(struct extctx_layout *extctx,
struct ctx_layout *sctx, unsigned size,
unsigned align, abi_ptr orig_sp)
@ -150,7 +130,7 @@ static void setup_sigframe(CPULoongArchState *env,
for (i = 0; i < 32; ++i) {
__put_user(env->fpr[i], &fpu_ctx->regs[i]);
}
__put_user(read_all_fcc(env), &fpu_ctx->fcc);
__put_user(read_fcc(env), &fpu_ctx->fcc);
__put_user(env->fcsr0, &fpu_ctx->fcsr);
/*
@ -216,7 +196,7 @@ static void restore_sigframe(CPULoongArchState *env,
__get_user(env->fpr[i], &fpu_ctx->regs[i]);
}
__get_user(fcc, &fpu_ctx->fcc);
write_all_fcc(env, fcc);
write_fcc(env, fcc);
__get_user(env->fcsr0, &fpu_ctx->fcsr);
restore_fp_status(env);
}

8
target/loongarch/cpu.c
View File

@ -661,6 +661,11 @@ static const struct SysemuCPUOps loongarch_sysemu_ops = {
};
#endif
static gchar *loongarch_gdb_arch_name(CPUState *cs)
{
return g_strdup("loongarch64");
}
static void loongarch_cpu_class_init(ObjectClass *c, void *data)
{
LoongArchCPUClass *lacc = LOONGARCH_CPU_CLASS(c);
@ -683,9 +688,10 @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_read_register = loongarch_cpu_gdb_read_register;
cc->gdb_write_register = loongarch_cpu_gdb_write_register;
cc->disas_set_info = loongarch_cpu_disas_set_info;
cc->gdb_num_core_regs = 34;
cc->gdb_num_core_regs = 35;
cc->gdb_core_xml_file = "loongarch-base64.xml";
cc->gdb_stop_before_watchpoint = true;
cc->gdb_arch_name = loongarch_gdb_arch_name;
#ifdef CONFIG_TCG
cc->tcg_ops = &loongarch_tcg_ops;

18
target/loongarch/cpu.h
View File

@ -47,11 +47,23 @@ FIELD(FCSR0, FLAGS, 16, 5)
FIELD(FCSR0, CAUSE, 24, 5)
#define GET_FP_CAUSE(REG) FIELD_EX32(REG, FCSR0, CAUSE)
#define SET_FP_CAUSE(REG, V) FIELD_DP32(REG, FCSR0, CAUSE, V)
#define SET_FP_CAUSE(REG, V) \
do { \
(REG) = FIELD_DP32(REG, FCSR0, CAUSE, V); \
} while (0)
#define GET_FP_ENABLES(REG) FIELD_EX32(REG, FCSR0, ENABLES)
#define SET_FP_ENABLES(REG, V) FIELD_DP32(REG, FCSR0, ENABLES, V)
#define SET_FP_ENABLES(REG, V) \
do { \
(REG) = FIELD_DP32(REG, FCSR0, ENABLES, V); \
} while (0)
#define GET_FP_FLAGS(REG) FIELD_EX32(REG, FCSR0, FLAGS)
#define SET_FP_FLAGS(REG, V) FIELD_DP32(REG, FCSR0, FLAGS, V)
#define SET_FP_FLAGS(REG, V) \
do { \
(REG) = FIELD_DP32(REG, FCSR0, FLAGS, V); \
} while (0)
#define UPDATE_FP_FLAGS(REG, V) \
do { \
(REG) |= FIELD_DP32(0, FCSR0, FLAGS, V); \

43
target/loongarch/gdbstub.c
View File

@ -11,6 +11,24 @@
#include "internals.h"
#include "exec/gdbstub.h"
uint64_t read_fcc(CPULoongArchState *env)
{
uint64_t ret = 0;
for (int i = 0; i < 8; ++i) {
ret |= (uint64_t)env->cf[i] << (i * 8);
}
return ret;
}
void write_fcc(CPULoongArchState *env, uint64_t val)
{
for (int i = 0; i < 8; ++i) {
env->cf[i] = (val >> (i * 8)) & 1;
}
}
int loongarch_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
LoongArchCPU *cpu = LOONGARCH_CPU(cs);
@ -19,8 +37,11 @@ int loongarch_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
if (0 <= n && n < 32) {
return gdb_get_regl(mem_buf, env->gpr[n]);
} else if (n == 32) {
return gdb_get_regl(mem_buf, env->pc);
/* orig_a0 */
return gdb_get_regl(mem_buf, 0);
} else if (n == 33) {
return gdb_get_regl(mem_buf, env->pc);
} else if (n == 34) {
return gdb_get_regl(mem_buf, env->CSR_BADV);
}
return 0;
@ -36,7 +57,7 @@ int loongarch_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
if (0 <= n && n < 32) {
env->gpr[n] = tmp;
length = sizeof(target_ulong);
} else if (n == 32) {
} else if (n == 33) {
env->pc = tmp;
length = sizeof(target_ulong);
}
@ -48,9 +69,10 @@ static int loongarch_gdb_get_fpu(CPULoongArchState *env,
{
if (0 <= n && n < 32) {
return gdb_get_reg64(mem_buf, env->fpr[n]);
} else if (32 <= n && n < 40) {
return gdb_get_reg8(mem_buf, env->cf[n - 32]);
} else if (n == 40) {
} else if (n == 32) {
uint64_t val = read_fcc(env);
return gdb_get_reg64(mem_buf, val);
} else if (n == 33) {
return gdb_get_reg32(mem_buf, env->fcsr0);
}
return 0;
@ -64,10 +86,11 @@ static int loongarch_gdb_set_fpu(CPULoongArchState *env,
if (0 <= n && n < 32) {
env->fpr[n] = ldq_p(mem_buf);
length = 8;
} else if (32 <= n && n < 40) {
env->cf[n - 32] = ldub_p(mem_buf);
length = 1;
} else if (n == 40) {
} else if (n == 32) {
uint64_t val = ldq_p(mem_buf);
write_fcc(env, val);
length = 8;
} else if (n == 33) {
env->fcsr0 = ldl_p(mem_buf);
length = 4;
}
@ -77,5 +100,5 @@ static int loongarch_gdb_set_fpu(CPULoongArchState *env,
void loongarch_cpu_register_gdb_regs_for_features(CPUState *cs)
{
gdb_register_coprocessor(cs, loongarch_gdb_get_fpu, loongarch_gdb_set_fpu,
41, "loongarch-fpu64.xml", 0);
41, "loongarch-fpu.xml", 0);
}

3
target/loongarch/internals.h
View File

@ -51,6 +51,9 @@ bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
#endif /* !CONFIG_USER_ONLY */
uint64_t read_fcc(CPULoongArchState *env);
void write_fcc(CPULoongArchState *env, uint64_t val);
int loongarch_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n);
int loongarch_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n);
void loongarch_cpu_register_gdb_regs_for_features(CPUState *cs);