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ppc/pnv: Implement the ChipTOD to Core transfer

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One of the functions of the ChipTOD is to transfer TOD to the Core
(aka PC - Pervasive Core) timebase facility.

The ChipTOD can be programmed with a target address to send the TOD
value to. The hardware implementation seems to perform this by
sending the TOD value to a SCOM address.

This implementation grabs the core directly and manipulates the
timebase facility state in the core. This is a hack, but it works
enough for now. A better implementation would implement the transfer
to the PnvCore xscom register and drive the timebase state machine
from there.

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
This commit is contained in:
Nicholas Piggin 2023-11-23 18:02:36 +10:00
parent de3ba0cc38
commit cde2ba34a9
5 changed files with 166 additions and 0 deletions
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15
hw/ppc/pnv.c
View File

@ -2121,6 +2121,21 @@ static void pnv_chip_class_init(ObjectClass *klass, void *data)
dc->desc = "PowerNV Chip";
}
PnvCore *pnv_chip_find_core(PnvChip *chip, uint32_t core_id)
{
int i;
for (i = 0; i < chip->nr_cores; i++) {
PnvCore *pc = chip->cores[i];
CPUCore *cc = CPU_CORE(pc);
if (cc->core_id == core_id) {
return pc;
}
}
return NULL;
}
PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir)
{
int i, j;

132
hw/ppc/pnv_chiptod.c
View File

@ -210,6 +210,79 @@ static void chiptod_power10_broadcast_ttype(PnvChipTOD *sender,
}
}
static PnvCore *pnv_chip_get_core_by_xscom_base(PnvChip *chip,
uint32_t xscom_base)
{
PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
int i;
for (i = 0; i < chip->nr_cores; i++) {
PnvCore *pc = chip->cores[i];
CPUCore *cc = CPU_CORE(pc);
int core_hwid = cc->core_id;
if (pcc->xscom_core_base(chip, core_hwid) == xscom_base) {
return pc;
}
}
return NULL;
}
static PnvCore *chiptod_power9_tx_ttype_target(PnvChipTOD *chiptod,
uint64_t val)
{
/*
* skiboot uses Core ID for P9, though SCOM should work too.
*/
if (val & PPC_BIT(35)) { /* SCOM addressing */
uint32_t addr = val >> 32;
uint32_t reg = addr & 0xfff;
if (reg != PC_TOD) {
qemu_log_mask(LOG_GUEST_ERROR, "pnv_chiptod: SCOM addressing: "
"unimplemented slave register 0x%" PRIx32 "\n", reg);
return NULL;
}
return pnv_chip_get_core_by_xscom_base(chiptod->chip, addr & ~0xfff);
} else { /* Core ID addressing */
uint32_t core_id = GETFIELD(TOD_TX_TTYPE_PIB_SLAVE_ADDR, val) & 0x1f;
return pnv_chip_find_core(chiptod->chip, core_id);
}
}
static PnvCore *chiptod_power10_tx_ttype_target(PnvChipTOD *chiptod,
uint64_t val)
{
/*
* skiboot uses SCOM for P10 because Core ID was unable to be made to
* work correctly. For this reason only SCOM addressing is implemented.
*/
if (val & PPC_BIT(35)) { /* SCOM addressing */
uint32_t addr = val >> 32;
uint32_t reg = addr & 0xfff;
if (reg != PC_TOD) {
qemu_log_mask(LOG_GUEST_ERROR, "pnv_chiptod: SCOM addressing: "
"unimplemented slave register 0x%" PRIx32 "\n", reg);
return NULL;
}
/*
* This may not deal with P10 big-core addressing at the moment.
* The big-core code in skiboot syncs small cores, but it targets
* the even PIR (first small-core) when syncing second small-core.
*/
return pnv_chip_get_core_by_xscom_base(chiptod->chip, addr & ~0xfff);
} else { /* Core ID addressing */
qemu_log_mask(LOG_UNIMP, "pnv_chiptod: TX TTYPE Core ID "
"addressing is not implemented for POWER10\n");
return NULL;
}
}
static void pnv_chiptod_xscom_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
@ -231,6 +304,22 @@ static void pnv_chiptod_xscom_write(void *opaque, hwaddr addr,
chiptod->pss_mss_ctrl_reg = val & PPC_BITMASK(0, 31);
break;
case TOD_TX_TTYPE_CTRL_REG:
/*
* This register sets the target of the TOD value transfer initiated
* by TOD_MOVE_TOD_TO_TB. The TOD is able to send the address to
* any target register, though in practice only the PC TOD register
* should be used. ChipTOD has a "SCOM addressing" mode which fully
* specifies the SCOM address, and a core-ID mode which uses the
* core ID to target the PC TOD for a given core.
*/
chiptod->slave_pc_target = pctc->tx_ttype_target(chiptod, val);
if (!chiptod->slave_pc_target) {
qemu_log_mask(LOG_GUEST_ERROR, "pnv_chiptod: xscom write reg"
" TOD_TX_TTYPE_CTRL_REG val 0x%" PRIx64
" invalid slave address\n", val);
}
break;
case TOD_ERROR_REG:
chiptod->tod_error &= ~val;
break;
@ -256,6 +345,47 @@ static void pnv_chiptod_xscom_write(void *opaque, hwaddr addr,
}
}
break;
case TOD_MOVE_TOD_TO_TB_REG:
/*
* XXX: it should be a cleaner model to have this drive a SCOM
* transaction to the target address, and implement the state machine
* in the PnvCore. For now, this hack makes things work.
*/
if (chiptod->tod_state != tod_running) {
qemu_log_mask(LOG_GUEST_ERROR, "pnv_chiptod: xscom write reg"
" TOD_MOVE_TOD_TO_TB_REG in bad state %d\n",
chiptod->tod_state);
} else if (!(val & PPC_BIT(0))) {
qemu_log_mask(LOG_GUEST_ERROR, "pnv_chiptod: xscom write reg"
" TOD_MOVE_TOD_TO_TB_REG with bad val 0x%" PRIx64"\n",
val);
} else if (chiptod->slave_pc_target == NULL) {
qemu_log_mask(LOG_GUEST_ERROR, "pnv_chiptod: xscom write reg"
" TOD_MOVE_TOD_TO_TB_REG with no slave target\n");
} else {
PowerPCCPU *cpu = chiptod->slave_pc_target->threads[0];
CPUPPCState *env = &cpu->env;
/*
* Moving TOD to TB will set the TB of all threads in a
* core, so skiboot only does this once per thread0, so
* that is where we keep the timebase state machine.
*
* It is likely possible for TBST to be driven from other
* threads in the core, but for now we only implement it for
* thread 0.
*/
if (env->pnv_tod_tbst.tb_ready_for_tod) {
env->pnv_tod_tbst.tod_sent_to_tb = 1;
} else {
qemu_log_mask(LOG_GUEST_ERROR, "pnv_chiptod: xscom write reg"
" TOD_MOVE_TOD_TO_TB_REG with TB not ready to"
" receive TOD\n");
}
}
break;
case TOD_START_TOD_REG:
if (chiptod->tod_state != tod_stopped) {
qemu_log_mask(LOG_GUEST_ERROR, "pnv_chiptod: LOAD_TOG_REG in "
@ -340,6 +470,7 @@ static void pnv_chiptod_power9_class_init(ObjectClass *klass, void *data)
xdc->dt_xscom = pnv_chiptod_power9_dt_xscom;
pctc->broadcast_ttype = chiptod_power9_broadcast_ttype;
pctc->tx_ttype_target = chiptod_power9_tx_ttype_target;
pctc->xscom_size = PNV_XSCOM_CHIPTOD_SIZE;
}
@ -375,6 +506,7 @@ static void pnv_chiptod_power10_class_init(ObjectClass *klass, void *data)
xdc->dt_xscom = pnv_chiptod_power10_dt_xscom;
pctc->broadcast_ttype = chiptod_power10_broadcast_ttype;
pctc->tx_ttype_target = chiptod_power10_tx_ttype_target;
pctc->xscom_size = PNV_XSCOM_CHIPTOD_SIZE;
}

2
include/hw/ppc/pnv.h
View File

@ -28,6 +28,7 @@
#define TYPE_PNV_CHIP "pnv-chip"
typedef struct PnvCore PnvCore;
typedef struct PnvChip PnvChip;
typedef struct Pnv8Chip Pnv8Chip;
typedef struct Pnv9Chip Pnv9Chip;
@ -56,6 +57,7 @@ DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER9,
DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER10,
TYPE_PNV_CHIP_POWER10)
PnvCore *pnv_chip_find_core(PnvChip *chip, uint32_t core_id);
PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir);
typedef struct PnvPHB PnvPHB;

4
include/hw/ppc/pnv_chiptod.h
View File

@ -25,6 +25,8 @@ enum tod_state {
tod_stopped = 1,
};
typedef struct PnvCore PnvCore;
struct PnvChipTOD {
DeviceState xd;
@ -36,12 +38,14 @@ struct PnvChipTOD {
enum tod_state tod_state;
uint64_t tod_error;
uint64_t pss_mss_ctrl_reg;
PnvCore *slave_pc_target;
};
struct PnvChipTODClass {
DeviceClass parent_class;
void (*broadcast_ttype)(PnvChipTOD *sender, uint32_t trigger);
PnvCore *(*tx_ttype_target)(PnvChipTOD *chiptod, uint64_t val);
int xscom_size;
};

13
target/ppc/cpu.h
View File

@ -1183,6 +1183,13 @@ DEXCR_ASPECT(SRAPD, 4)
DEXCR_ASPECT(NPHIE, 5)
DEXCR_ASPECT(PHIE, 6)
/*****************************************************************************/
/* PowerNV ChipTOD and TimeBase State Machine */
struct pnv_tod_tbst {
int tb_ready_for_tod; /* core TB ready to receive TOD from chiptod */
int tod_sent_to_tb; /* chiptod sent TOD to the core TB */
};
/*****************************************************************************/
/* The whole PowerPC CPU context */
@ -1258,6 +1265,12 @@ struct CPUArchState {
uint32_t tlb_need_flush; /* Delayed flush needed */
#define TLB_NEED_LOCAL_FLUSH 0x1
#define TLB_NEED_GLOBAL_FLUSH 0x2
#if defined(TARGET_PPC64)
/* PowerNV chiptod / timebase facility state. */
/* Would be nice to put these into PnvCore */
struct pnv_tod_tbst pnv_tod_tbst;
#endif
#endif
/* Other registers */