Merge patch series "make write_misa a no-op and FEATURE_* cleanups"
Daniel Henrique Barboza <dbarboza@ventanamicro.com> says: The RISCV_FEATURES_* enum and the CPUArchState::features attribute were introduced 4+ years ago, as a way to retrieve the enabled hart features that aren't represented via MISA CSR bits. Time passed on, and RISCVCPUConfig was introduced. With it, we now have a centralized way of reading all hart features that are enabled/disabled by the user and the board. All recent features are reading their correspondent cpu->cfg.X flag. All but the 5 features in the RISCV_FEATURE_* enum. These features are still operating in the same way: set it during riscv_cpu_realize() using their cpu->cfg value, read it using riscv_feature() when needed. There is nothing special about them in comparison with all the other features and extensions to justify this special handling. This series then is doing two things: first we're actually allowing users to write the MISA CSR if they so choose. Then we're deprecate each RISC_FEATURE_* usage until, in patch 11, we remove everything related to it. All 5 existing RISCV_FEATURE_* features will be handled as everyone else. * b4-shazam-merge: target/riscv/cpu: remove CPUArchState::features and friends target/riscv: remove RISCV_FEATURE_MMU hw/riscv/virt.c: do not use RISCV_FEATURE_MMU in create_fdt_socket_cpus() target/riscv: remove RISCV_FEATURE_PMP target/riscv: remove RISCV_FEATURE_EPMP target/riscv/cpu.c: error out if EPMP is enabled without PMP target/riscv: remove RISCV_FEATURE_DEBUG target/riscv: allow MISA writes as experimental target/riscv: do not mask unsupported QEMU extensions in write_misa() target/riscv: introduce riscv_cpu_cfg() Message-ID: <20230222185205.355361-1-dbarboza@ventanamicro.com> [Palmer: use the text from the v1] Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
This commit is contained in:
commit
d3e6d5762b
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@ -232,20 +232,21 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket,
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bool is_32_bit = riscv_is_32bit(&s->soc[0]);
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for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) {
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RISCVCPU *cpu_ptr = &s->soc[socket].harts[cpu];
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cpu_phandle = (*phandle)++;
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cpu_name = g_strdup_printf("/cpus/cpu@%d",
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s->soc[socket].hartid_base + cpu);
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qemu_fdt_add_subnode(ms->fdt, cpu_name);
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if (riscv_feature(&s->soc[socket].harts[cpu].env,
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RISCV_FEATURE_MMU)) {
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if (cpu_ptr->cfg.mmu) {
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qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type",
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(is_32_bit) ? "riscv,sv32" : "riscv,sv48");
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} else {
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qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type",
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"riscv,none");
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}
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name = riscv_isa_string(&s->soc[socket].harts[cpu]);
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name = riscv_isa_string(cpu_ptr);
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qemu_fdt_setprop_string(ms->fdt, cpu_name, "riscv,isa", name);
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g_free(name);
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qemu_fdt_setprop_string(ms->fdt, cpu_name, "compatible", "riscv");
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@ -637,7 +637,7 @@ static void riscv_cpu_reset_hold(Object *obj)
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set_default_nan_mode(1, &env->fp_status);
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#ifndef CONFIG_USER_ONLY
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if (riscv_feature(env, RISCV_FEATURE_DEBUG)) {
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if (cpu->cfg.debug) {
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riscv_trigger_init(env);
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}
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@ -919,24 +919,13 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
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}
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}
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if (cpu->cfg.mmu) {
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riscv_set_feature(env, RISCV_FEATURE_MMU);
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}
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if (cpu->cfg.pmp) {
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riscv_set_feature(env, RISCV_FEATURE_PMP);
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if (cpu->cfg.epmp && !cpu->cfg.pmp) {
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/*
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* Enhanced PMP should only be available
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* on harts with PMP support
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*/
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if (cpu->cfg.epmp) {
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riscv_set_feature(env, RISCV_FEATURE_EPMP);
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}
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}
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if (cpu->cfg.debug) {
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riscv_set_feature(env, RISCV_FEATURE_DEBUG);
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error_setg(errp, "Invalid configuration: EPMP requires PMP support");
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return;
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}
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@ -1210,6 +1199,12 @@ static Property riscv_cpu_properties[] = {
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DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false),
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DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false),
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/*
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* write_misa() is marked as experimental for now so mark
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* it with -x and default to 'false'.
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*/
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DEFINE_PROP_BOOL("x-misa-w", RISCVCPU, cfg.misa_w, false),
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DEFINE_PROP_END_OF_LIST(),
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};
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@ -81,17 +81,6 @@
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#define RVH RV('H')
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#define RVJ RV('J')
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/* S extension denotes that Supervisor mode exists, however it is possible
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to have a core that support S mode but does not have an MMU and there
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is currently no bit in misa to indicate whether an MMU exists or not
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so a cpu features bitfield is required, likewise for optional PMP support */
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enum {
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RISCV_FEATURE_MMU,
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RISCV_FEATURE_PMP,
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RISCV_FEATURE_EPMP,
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RISCV_FEATURE_MISA,
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RISCV_FEATURE_DEBUG
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};
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/* Privileged specification version */
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enum {
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@ -186,8 +175,6 @@ struct CPUArchState {
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/* 128-bit helpers upper part return value */
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target_ulong retxh;
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uint32_t features;
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#ifdef CONFIG_USER_ONLY
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uint32_t elf_flags;
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#endif
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@ -498,6 +485,7 @@ struct RISCVCPUConfig {
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bool pmp;
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bool epmp;
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bool debug;
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bool misa_w;
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bool short_isa_string;
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};
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@ -535,16 +523,6 @@ static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
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return (env->misa_ext & ext) != 0;
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}
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static inline bool riscv_feature(CPURISCVState *env, int feature)
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{
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return env->features & (1ULL << feature);
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}
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static inline void riscv_set_feature(CPURISCVState *env, int feature)
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{
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env->features |= (1ULL << feature);
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}
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#include "cpu_user.h"
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extern const char * const riscv_int_regnames[];
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@ -654,6 +632,11 @@ static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env)
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#endif
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#define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env)))
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static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env)
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{
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return &env_archcpu(env)->cfg;
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}
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#if defined(TARGET_RISCV32)
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#define cpu_recompute_xl(env) ((void)(env), MXL_RV32)
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#else
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@ -105,7 +105,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
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flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_VS,
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get_field(env->mstatus_hs, MSTATUS_VS));
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}
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if (riscv_feature(env, RISCV_FEATURE_DEBUG) && !icount_enabled()) {
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if (cpu->cfg.debug && !icount_enabled()) {
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flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled);
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}
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#endif
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@ -706,7 +706,7 @@ static int get_physical_address_pmp(CPURISCVState *env, int *prot,
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pmp_priv_t pmp_priv;
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int pmp_index = -1;
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if (!riscv_feature(env, RISCV_FEATURE_PMP)) {
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if (!riscv_cpu_cfg(env)->pmp) {
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*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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return TRANSLATE_SUCCESS;
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}
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@ -796,7 +796,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
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mode = PRV_U;
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}
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if (mode == PRV_M || !riscv_feature(env, RISCV_FEATURE_MMU)) {
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if (mode == PRV_M || !riscv_cpu_cfg(env)->mmu) {
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*physical = addr;
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*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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return TRANSLATE_SUCCESS;
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@ -419,7 +419,7 @@ static int aia_hmode32(CPURISCVState *env, int csrno)
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static RISCVException pmp(CPURISCVState *env, int csrno)
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{
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if (riscv_feature(env, RISCV_FEATURE_PMP)) {
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if (riscv_cpu_cfg(env)->pmp) {
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return RISCV_EXCP_NONE;
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}
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@ -428,7 +428,7 @@ static RISCVException pmp(CPURISCVState *env, int csrno)
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static RISCVException epmp(CPURISCVState *env, int csrno)
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{
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if (env->priv == PRV_M && riscv_feature(env, RISCV_FEATURE_EPMP)) {
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if (env->priv == PRV_M && riscv_cpu_cfg(env)->epmp) {
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return RISCV_EXCP_NONE;
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}
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@ -437,7 +437,7 @@ static RISCVException epmp(CPURISCVState *env, int csrno)
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static RISCVException debug(CPURISCVState *env, int csrno)
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{
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if (riscv_feature(env, RISCV_FEATURE_DEBUG)) {
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if (riscv_cpu_cfg(env)->debug) {
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return RISCV_EXCP_NONE;
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}
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@ -1329,7 +1329,7 @@ static RISCVException read_misa(CPURISCVState *env, int csrno,
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static RISCVException write_misa(CPURISCVState *env, int csrno,
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target_ulong val)
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{
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if (!riscv_feature(env, RISCV_FEATURE_MISA)) {
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if (!riscv_cpu_cfg(env)->misa_w) {
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/* drop write to misa */
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return RISCV_EXCP_NONE;
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}
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@ -1356,9 +1356,6 @@ static RISCVException write_misa(CPURISCVState *env, int csrno,
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/* Mask extensions that are not supported by this hart */
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val &= env->misa_ext_mask;
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/* Mask extensions that are not supported by QEMU */
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val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU | RVV);
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/* 'D' depends on 'F', so clear 'D' if 'F' is not present */
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if ((val & RVD) && !(val & RVF)) {
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val &= ~RVD;
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@ -2624,7 +2621,7 @@ static RISCVException rmw_siph(CPURISCVState *env, int csrno,
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static RISCVException read_satp(CPURISCVState *env, int csrno,
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target_ulong *val)
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{
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if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
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if (!riscv_cpu_cfg(env)->mmu) {
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*val = 0;
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return RISCV_EXCP_NONE;
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}
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@ -2643,7 +2640,7 @@ static RISCVException write_satp(CPURISCVState *env, int csrno,
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{
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target_ulong vm, mask;
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if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
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if (!riscv_cpu_cfg(env)->mmu) {
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return RISCV_EXCP_NONE;
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}
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@ -27,9 +27,8 @@
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static bool pmp_needed(void *opaque)
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{
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RISCVCPU *cpu = opaque;
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CPURISCVState *env = &cpu->env;
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return riscv_feature(env, RISCV_FEATURE_PMP);
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return cpu->cfg.pmp;
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}
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static int pmp_post_load(void *opaque, int version_id)
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@ -226,9 +225,8 @@ static const VMStateDescription vmstate_kvmtimer = {
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static bool debug_needed(void *opaque)
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{
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RISCVCPU *cpu = opaque;
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CPURISCVState *env = &cpu->env;
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return riscv_feature(env, RISCV_FEATURE_DEBUG);
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return cpu->cfg.debug;
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}
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static int debug_post_load(void *opaque, int version_id)
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@ -333,8 +331,8 @@ static const VMStateDescription vmstate_pmu_ctr_state = {
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const VMStateDescription vmstate_riscv_cpu = {
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.name = "cpu",
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.version_id = 6,
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.minimum_version_id = 6,
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.version_id = 7,
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.minimum_version_id = 7,
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.post_load = riscv_cpu_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
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@ -353,7 +351,6 @@ const VMStateDescription vmstate_riscv_cpu = {
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VMSTATE_UINT32(env.misa_ext, RISCVCPU),
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VMSTATE_UINT32(env.misa_mxl_max, RISCVCPU),
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VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU),
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VMSTATE_UINT32(env.features, RISCVCPU),
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VMSTATE_UINTTL(env.priv, RISCVCPU),
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VMSTATE_UINTTL(env.virt, RISCVCPU),
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VMSTATE_UINT64(env.resetvec, RISCVCPU),
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@ -218,7 +218,7 @@ void hmp_info_mem(Monitor *mon, const QDict *qdict)
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return;
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}
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if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
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if (!riscv_cpu_cfg(env)->mmu) {
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monitor_printf(mon, "S-mode MMU unavailable\n");
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return;
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}
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@ -195,7 +195,7 @@ target_ulong helper_mret(CPURISCVState *env)
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uint64_t mstatus = env->mstatus;
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target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP);
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if (riscv_feature(env, RISCV_FEATURE_PMP) &&
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if (riscv_cpu_cfg(env)->pmp &&
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!pmp_get_num_rules(env) && (prev_priv != PRV_M)) {
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riscv_raise_exception(env, RISCV_EXCP_INST_ACCESS_FAULT, GETPC());
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}
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@ -88,7 +88,7 @@ static void pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val)
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if (pmp_index < MAX_RISCV_PMPS) {
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bool locked = true;
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if (riscv_feature(env, RISCV_FEATURE_EPMP)) {
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if (riscv_cpu_cfg(env)->epmp) {
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/* mseccfg.RLB is set */
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if (MSECCFG_RLB_ISSET(env)) {
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locked = false;
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@ -239,7 +239,7 @@ static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr,
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{
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bool ret;
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if (riscv_feature(env, RISCV_FEATURE_EPMP)) {
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if (riscv_cpu_cfg(env)->epmp) {
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if (MSECCFG_MMWP_ISSET(env)) {
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/*
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* The Machine Mode Whitelist Policy (mseccfg.MMWP) is set
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@ -265,7 +265,7 @@ static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr,
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}
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}
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if ((!riscv_feature(env, RISCV_FEATURE_PMP)) || (mode == PRV_M)) {
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if (!riscv_cpu_cfg(env)->pmp || (mode == PRV_M)) {
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/*
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* Privileged spec v1.10 states if HW doesn't implement any PMP entry
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* or no PMP entry matches an M-Mode access, the access succeeds.
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@ -315,7 +315,7 @@ int pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
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}
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if (size == 0) {
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if (riscv_feature(env, RISCV_FEATURE_MMU)) {
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if (riscv_cpu_cfg(env)->mmu) {
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/*
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* If size is unknown (0), assume that all bytes
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* from addr to the end of the page will be accessed.
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