target/arm: Decode aa64 armv8.1 scalar three same extra
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180228193125.20577-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -5,7 +5,7 @@ obj-$(call land,$(CONFIG_KVM),$(call lnot,$(TARGET_AARCH64))) += kvm32.o
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obj-$(call land,$(CONFIG_KVM),$(TARGET_AARCH64)) += kvm64.o
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obj-$(call lnot,$(CONFIG_KVM)) += kvm-stub.o
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obj-y += translate.o op_helper.o helper.o cpu.o
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obj-y += neon_helper.o iwmmxt_helper.o
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obj-y += neon_helper.o iwmmxt_helper.o vec_helper.o
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obj-y += gdbstub.o
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obj-$(TARGET_AARCH64) += cpu64.o translate-a64.o helper-a64.o gdbstub64.o
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obj-y += crypto_helper.o
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@ -365,8 +365,12 @@ DEF_HELPER_FLAGS_1(neon_rbit_u8, TCG_CALL_NO_RWG_SE, i32, i32)
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DEF_HELPER_3(neon_qdmulh_s16, i32, env, i32, i32)
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DEF_HELPER_3(neon_qrdmulh_s16, i32, env, i32, i32)
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DEF_HELPER_4(neon_qrdmlah_s16, i32, env, i32, i32, i32)
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DEF_HELPER_4(neon_qrdmlsh_s16, i32, env, i32, i32, i32)
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DEF_HELPER_3(neon_qdmulh_s32, i32, env, i32, i32)
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DEF_HELPER_3(neon_qrdmulh_s32, i32, env, i32, i32)
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DEF_HELPER_4(neon_qrdmlah_s32, i32, env, s32, s32, s32)
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DEF_HELPER_4(neon_qrdmlsh_s32, i32, env, s32, s32, s32)
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DEF_HELPER_1(neon_narrow_u8, i32, i64)
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DEF_HELPER_1(neon_narrow_u16, i32, i64)
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@ -7971,6 +7971,89 @@ static void disas_simd_scalar_three_reg_same_fp16(DisasContext *s,
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tcg_temp_free_ptr(fpst);
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}
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/* AdvSIMD scalar three same extra
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* 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
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* +-----+---+-----------+------+---+------+---+--------+---+----+----+
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* | 0 1 | U | 1 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
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* +-----+---+-----------+------+---+------+---+--------+---+----+----+
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*/
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static void disas_simd_scalar_three_reg_same_extra(DisasContext *s,
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uint32_t insn)
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{
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int rd = extract32(insn, 0, 5);
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int rn = extract32(insn, 5, 5);
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int opcode = extract32(insn, 11, 4);
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int rm = extract32(insn, 16, 5);
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int size = extract32(insn, 22, 2);
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bool u = extract32(insn, 29, 1);
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TCGv_i32 ele1, ele2, ele3;
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TCGv_i64 res;
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int feature;
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switch (u * 16 + opcode) {
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case 0x10: /* SQRDMLAH (vector) */
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case 0x11: /* SQRDMLSH (vector) */
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if (size != 1 && size != 2) {
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unallocated_encoding(s);
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return;
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}
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feature = ARM_FEATURE_V8_RDM;
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break;
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default:
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unallocated_encoding(s);
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return;
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}
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if (!arm_dc_feature(s, feature)) {
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unallocated_encoding(s);
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return;
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}
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if (!fp_access_check(s)) {
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return;
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}
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/* Do a single operation on the lowest element in the vector.
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* We use the standard Neon helpers and rely on 0 OP 0 == 0
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* with no side effects for all these operations.
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* OPTME: special-purpose helpers would avoid doing some
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* unnecessary work in the helper for the 16 bit cases.
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*/
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ele1 = tcg_temp_new_i32();
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ele2 = tcg_temp_new_i32();
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ele3 = tcg_temp_new_i32();
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read_vec_element_i32(s, ele1, rn, 0, size);
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read_vec_element_i32(s, ele2, rm, 0, size);
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read_vec_element_i32(s, ele3, rd, 0, size);
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switch (opcode) {
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case 0x0: /* SQRDMLAH */
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if (size == 1) {
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gen_helper_neon_qrdmlah_s16(ele3, cpu_env, ele1, ele2, ele3);
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} else {
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gen_helper_neon_qrdmlah_s32(ele3, cpu_env, ele1, ele2, ele3);
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}
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break;
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case 0x1: /* SQRDMLSH */
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if (size == 1) {
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gen_helper_neon_qrdmlsh_s16(ele3, cpu_env, ele1, ele2, ele3);
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} else {
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gen_helper_neon_qrdmlsh_s32(ele3, cpu_env, ele1, ele2, ele3);
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}
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break;
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default:
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g_assert_not_reached();
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}
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tcg_temp_free_i32(ele1);
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tcg_temp_free_i32(ele2);
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res = tcg_temp_new_i64();
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tcg_gen_extu_i32_i64(res, ele3);
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tcg_temp_free_i32(ele3);
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write_fp_dreg(s, rd, res);
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tcg_temp_free_i64(res);
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}
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static void handle_2misc_64(DisasContext *s, int opcode, bool u,
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TCGv_i64 tcg_rd, TCGv_i64 tcg_rn,
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TCGv_i32 tcg_rmode, TCGv_ptr tcg_fpstatus)
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@ -12798,6 +12881,7 @@ static const AArch64DecodeTable data_proc_simd[] = {
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{ 0x0e000800, 0xbf208c00, disas_simd_zip_trn },
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{ 0x2e000000, 0xbf208400, disas_simd_ext },
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{ 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same },
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{ 0x5e008400, 0xdf208400, disas_simd_scalar_three_reg_same_extra },
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{ 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff },
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{ 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc },
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{ 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise },
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109
target/arm/vec_helper.c
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109
target/arm/vec_helper.c
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@ -0,0 +1,109 @@
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/*
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* ARM AdvSIMD / SVE Vector Operations
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*
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* Copyright (c) 2018 Linaro
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "exec/helper-proto.h"
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#include "tcg/tcg-gvec-desc.h"
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#define SET_QC() env->vfp.xregs[ARM_VFP_FPSCR] |= CPSR_Q
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/* Signed saturating rounding doubling multiply-accumulate high half, 16-bit */
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static uint16_t inl_qrdmlah_s16(CPUARMState *env, int16_t src1,
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int16_t src2, int16_t src3)
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{
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/* Simplify:
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* = ((a3 << 16) + ((e1 * e2) << 1) + (1 << 15)) >> 16
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* = ((a3 << 15) + (e1 * e2) + (1 << 14)) >> 15
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*/
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int32_t ret = (int32_t)src1 * src2;
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ret = ((int32_t)src3 << 15) + ret + (1 << 14);
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ret >>= 15;
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if (ret != (int16_t)ret) {
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SET_QC();
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ret = (ret < 0 ? -0x8000 : 0x7fff);
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}
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return ret;
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}
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uint32_t HELPER(neon_qrdmlah_s16)(CPUARMState *env, uint32_t src1,
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uint32_t src2, uint32_t src3)
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{
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uint16_t e1 = inl_qrdmlah_s16(env, src1, src2, src3);
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uint16_t e2 = inl_qrdmlah_s16(env, src1 >> 16, src2 >> 16, src3 >> 16);
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return deposit32(e1, 16, 16, e2);
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}
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/* Signed saturating rounding doubling multiply-subtract high half, 16-bit */
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static uint16_t inl_qrdmlsh_s16(CPUARMState *env, int16_t src1,
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int16_t src2, int16_t src3)
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{
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/* Similarly, using subtraction:
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* = ((a3 << 16) - ((e1 * e2) << 1) + (1 << 15)) >> 16
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* = ((a3 << 15) - (e1 * e2) + (1 << 14)) >> 15
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*/
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int32_t ret = (int32_t)src1 * src2;
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ret = ((int32_t)src3 << 15) - ret + (1 << 14);
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ret >>= 15;
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if (ret != (int16_t)ret) {
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SET_QC();
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ret = (ret < 0 ? -0x8000 : 0x7fff);
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}
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return ret;
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}
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uint32_t HELPER(neon_qrdmlsh_s16)(CPUARMState *env, uint32_t src1,
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uint32_t src2, uint32_t src3)
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{
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uint16_t e1 = inl_qrdmlsh_s16(env, src1, src2, src3);
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uint16_t e2 = inl_qrdmlsh_s16(env, src1 >> 16, src2 >> 16, src3 >> 16);
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return deposit32(e1, 16, 16, e2);
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}
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/* Signed saturating rounding doubling multiply-accumulate high half, 32-bit */
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uint32_t HELPER(neon_qrdmlah_s32)(CPUARMState *env, int32_t src1,
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int32_t src2, int32_t src3)
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{
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/* Simplify similarly to int_qrdmlah_s16 above. */
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int64_t ret = (int64_t)src1 * src2;
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ret = ((int64_t)src3 << 31) + ret + (1 << 30);
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ret >>= 31;
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if (ret != (int32_t)ret) {
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SET_QC();
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ret = (ret < 0 ? INT32_MIN : INT32_MAX);
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}
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return ret;
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}
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/* Signed saturating rounding doubling multiply-subtract high half, 32-bit */
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uint32_t HELPER(neon_qrdmlsh_s32)(CPUARMState *env, int32_t src1,
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int32_t src2, int32_t src3)
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{
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/* Simplify similarly to int_qrdmlsh_s16 above. */
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int64_t ret = (int64_t)src1 * src2;
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ret = ((int64_t)src3 << 31) - ret + (1 << 30);
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ret >>= 31;
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if (ret != (int32_t)ret) {
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SET_QC();
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ret = (ret < 0 ? INT32_MIN : INT32_MAX);
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}
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return ret;
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}
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