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target-arm queue: 

* fix minimum RAM check warning on xlnx-ep108
  * remove unused define from aarch64-linux-user.mak config
  * don't mask out bits [47:40] in ARMv8 LPAE descriptors
  * correct unallocated instruction checks for ldst_excl
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Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20151124' into staging

target-arm queue:
 * fix minimum RAM check warning on xlnx-ep108
 * remove unused define from aarch64-linux-user.mak config
 * don't mask out bits [47:40] in ARMv8 LPAE descriptors
 * correct unallocated instruction checks for ldst_excl

# gpg: Signature made Tue 24 Nov 2015 14:17:10 GMT using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>"
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"

* remotes/pmaydell/tags/pull-target-arm-20151124:
  target-arm/translate-a64.c: Correct unallocated checks for ldst_excl
  target-arm: Don't mask out bits [47:40] in LPAE descriptors for v8
  default-configs/aarch64-linux-user.mak: Remove unused define
  xlnx-ep108: Fix minimum RAM check

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2015-11-24 14:22:37 +00:00
parent 229c0372cf e14f0eb12f
commit d9636b6c2b
4 changed files with 14 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
default-configs/aarch64-linux-user.mak
View File

@ -1,3 +1 @@
# Default configuration for aarch64-linux-user
CONFIG_GDBSTUB_XML=y

2
hw/arm/xlnx-ep108.c
View File

@ -51,7 +51,7 @@ static void xlnx_ep108_init(MachineState *machine)
machine->ram_size = EP108_MAX_RAM_SIZE;
}
if (machine->ram_size <= 0x08000000) {
if (machine->ram_size < 0x08000000) {
qemu_log("WARNING: RAM size " RAM_ADDR_FMT " is small for EP108",
machine->ram_size);
}

12
target-arm/helper.c
View File

@ -6642,6 +6642,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
int ap, ns, xn, pxn;
uint32_t el = regime_el(env, mmu_idx);
bool ttbr1_valid = true;
uint64_t descaddrmask;
/* TODO:
* This code does not handle the different format TCR for VTCR_EL2.
@ -6831,6 +6832,15 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
descaddr = extract64(ttbr, 0, 48);
descaddr &= ~((1ULL << (inputsize - (stride * (4 - level)))) - 1);
/* The address field in the descriptor goes up to bit 39 for ARMv7
* but up to bit 47 for ARMv8.
*/
if (arm_feature(env, ARM_FEATURE_V8)) {
descaddrmask = 0xfffffffff000ULL;
} else {
descaddrmask = 0xfffffff000ULL;
}
/* Secure accesses start with the page table in secure memory and
* can be downgraded to non-secure at any step. Non-secure accesses
* remain non-secure. We implement this by just ORing in the NSTable/NS
@ -6854,7 +6864,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
/* Invalid, or the Reserved level 3 encoding */
goto do_fault;
}
descaddr = descriptor & 0xfffffff000ULL;
descaddr = descriptor & descaddrmask;
if ((descriptor & 2) && (level < 3)) {
/* Table entry. The top five bits are attributes which may

15
target-arm/translate-a64.c
View File

@ -1816,9 +1816,6 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
* o2: 0 -> exclusive, 1 -> not
* o1: 0 -> single register, 1 -> register pair
* o0: 1 -> load-acquire/store-release, 0 -> not
*
* o0 == 0 AND o2 == 1 is un-allocated
* o1 == 1 is un-allocated except for 32 and 64 bit sizes
*/
static void disas_ldst_excl(DisasContext *s, uint32_t insn)
{
@ -1833,7 +1830,8 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
int size = extract32(insn, 30, 2);
TCGv_i64 tcg_addr;
if ((!is_excl && !is_lasr) ||
if ((!is_excl && !is_pair && !is_lasr) ||
(!is_excl && is_pair) ||
(is_pair && size < 2)) {
unallocated_encoding(s);
return;
@ -1862,15 +1860,6 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
} else {
do_gpr_ld(s, tcg_rt, tcg_addr, size, false, false);
}
if (is_pair) {
TCGv_i64 tcg_rt2 = cpu_reg(s, rt);
tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size);
if (is_store) {
do_gpr_st(s, tcg_rt2, tcg_addr, size);
} else {
do_gpr_ld(s, tcg_rt2, tcg_addr, size, false, false);
}
}
}
}