target-arm queue:
* fix minimum RAM check warning on xlnx-ep108 * remove unused define from aarch64-linux-user.mak config * don't mask out bits [47:40] in ARMv8 LPAE descriptors * correct unallocated instruction checks for ldst_excl -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABCAAGBQJWVHFmAAoJEDwlJe0UNgze29AP+QELaOZcUxl8bAjG9PdkAcQX /xyD9YHUK4GK/bSJCgKIdwDOsiiQ+78pA/Rubmbhuph4Nl9ggcAzwzJZjaMWf8HX tOYeBdqg0ykq1EX1tJRzvaQRxwDMOLqZQa2+sSYYCgmZO8pBKeBhbQ0RkXQ7OYH0 A2LijXqE0Swfyvr/k1mghafcGlKUeQ+8uI59WaBaDn4BsoBp/LHjQTkujrrSkgog FOHFBXT8KrxKs9Uhu/rfaQMXfWiykTBQLbzgKd9d3N4KlB1GzdwVarsY05RYy+jY d2PYfu48QlC2GaNm4a3qxewKDUgzBg9x/UB/rbPpO47mySlGhRxeoUkjWYsfr18+ 4qWDm3B8brHv72+iOP4Wiv+nElTrA5N74TnwJnn7Q9epoISnaDALbix9rV8kiLrk PrivIid/DuVyu0RG7tFXXjxvKKYNparHuIcOs2SiX1BRuA7wc+OW5irrb1gHAkv+ 3tLyf3RJzNRu/0BI1QoCWgtONam5f5N+GabnoLBe/k4J9yK3N7xRtvO+aGcL4ztH gVO/+HpEBun5TiGskRsmATG4QY4VC2GEEtbCp1uysAEsuZJY5oHzkX60MYd3y5Xj YGddCAkJvBuboNWn+8RzNkRHJI6TJS+POAy+o6pza/NVyt/wD7ozph1DKXtl1nDT NHCA4nO/6LY0t7eumMUT =oaU/ -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20151124' into staging target-arm queue: * fix minimum RAM check warning on xlnx-ep108 * remove unused define from aarch64-linux-user.mak config * don't mask out bits [47:40] in ARMv8 LPAE descriptors * correct unallocated instruction checks for ldst_excl # gpg: Signature made Tue 24 Nov 2015 14:17:10 GMT using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" * remotes/pmaydell/tags/pull-target-arm-20151124: target-arm/translate-a64.c: Correct unallocated checks for ldst_excl target-arm: Don't mask out bits [47:40] in LPAE descriptors for v8 default-configs/aarch64-linux-user.mak: Remove unused define xlnx-ep108: Fix minimum RAM check Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
d9636b6c2b
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@ -1,3 +1 @@
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# Default configuration for aarch64-linux-user
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# Default configuration for aarch64-linux-user
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CONFIG_GDBSTUB_XML=y
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@ -51,7 +51,7 @@ static void xlnx_ep108_init(MachineState *machine)
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machine->ram_size = EP108_MAX_RAM_SIZE;
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machine->ram_size = EP108_MAX_RAM_SIZE;
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}
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}
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if (machine->ram_size <= 0x08000000) {
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if (machine->ram_size < 0x08000000) {
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qemu_log("WARNING: RAM size " RAM_ADDR_FMT " is small for EP108",
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qemu_log("WARNING: RAM size " RAM_ADDR_FMT " is small for EP108",
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machine->ram_size);
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machine->ram_size);
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}
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}
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@ -6642,6 +6642,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
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int ap, ns, xn, pxn;
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int ap, ns, xn, pxn;
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uint32_t el = regime_el(env, mmu_idx);
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uint32_t el = regime_el(env, mmu_idx);
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bool ttbr1_valid = true;
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bool ttbr1_valid = true;
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uint64_t descaddrmask;
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/* TODO:
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/* TODO:
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* This code does not handle the different format TCR for VTCR_EL2.
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* This code does not handle the different format TCR for VTCR_EL2.
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@ -6831,6 +6832,15 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
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descaddr = extract64(ttbr, 0, 48);
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descaddr = extract64(ttbr, 0, 48);
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descaddr &= ~((1ULL << (inputsize - (stride * (4 - level)))) - 1);
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descaddr &= ~((1ULL << (inputsize - (stride * (4 - level)))) - 1);
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/* The address field in the descriptor goes up to bit 39 for ARMv7
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* but up to bit 47 for ARMv8.
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*/
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if (arm_feature(env, ARM_FEATURE_V8)) {
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descaddrmask = 0xfffffffff000ULL;
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} else {
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descaddrmask = 0xfffffff000ULL;
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}
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/* Secure accesses start with the page table in secure memory and
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/* Secure accesses start with the page table in secure memory and
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* can be downgraded to non-secure at any step. Non-secure accesses
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* can be downgraded to non-secure at any step. Non-secure accesses
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* remain non-secure. We implement this by just ORing in the NSTable/NS
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* remain non-secure. We implement this by just ORing in the NSTable/NS
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@ -6854,7 +6864,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
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/* Invalid, or the Reserved level 3 encoding */
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/* Invalid, or the Reserved level 3 encoding */
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goto do_fault;
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goto do_fault;
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}
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}
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descaddr = descriptor & 0xfffffff000ULL;
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descaddr = descriptor & descaddrmask;
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if ((descriptor & 2) && (level < 3)) {
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if ((descriptor & 2) && (level < 3)) {
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/* Table entry. The top five bits are attributes which may
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/* Table entry. The top five bits are attributes which may
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@ -1816,9 +1816,6 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
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* o2: 0 -> exclusive, 1 -> not
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* o2: 0 -> exclusive, 1 -> not
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* o1: 0 -> single register, 1 -> register pair
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* o1: 0 -> single register, 1 -> register pair
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* o0: 1 -> load-acquire/store-release, 0 -> not
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* o0: 1 -> load-acquire/store-release, 0 -> not
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*
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* o0 == 0 AND o2 == 1 is un-allocated
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* o1 == 1 is un-allocated except for 32 and 64 bit sizes
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*/
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*/
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static void disas_ldst_excl(DisasContext *s, uint32_t insn)
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static void disas_ldst_excl(DisasContext *s, uint32_t insn)
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{
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{
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@ -1833,7 +1830,8 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
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int size = extract32(insn, 30, 2);
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int size = extract32(insn, 30, 2);
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TCGv_i64 tcg_addr;
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TCGv_i64 tcg_addr;
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if ((!is_excl && !is_lasr) ||
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if ((!is_excl && !is_pair && !is_lasr) ||
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(!is_excl && is_pair) ||
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(is_pair && size < 2)) {
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(is_pair && size < 2)) {
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unallocated_encoding(s);
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unallocated_encoding(s);
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return;
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return;
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@ -1862,15 +1860,6 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
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} else {
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} else {
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do_gpr_ld(s, tcg_rt, tcg_addr, size, false, false);
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do_gpr_ld(s, tcg_rt, tcg_addr, size, false, false);
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}
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}
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if (is_pair) {
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TCGv_i64 tcg_rt2 = cpu_reg(s, rt);
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tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size);
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if (is_store) {
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do_gpr_st(s, tcg_rt2, tcg_addr, size);
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} else {
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do_gpr_ld(s, tcg_rt2, tcg_addr, size, false, false);
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}
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}
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}
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}
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}
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}
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