pull-loongarch-20230616
-----BEGIN PGP SIGNATURE----- iLMEAAEIAB0WIQS4/x2g0v3LLaCcbCxAov/yOSY+3wUCZIwysgAKCRBAov/yOSY+ 39FYA/465KtY2jDt4xG6AdwZDHckfxZQWlrfhyZvtapOkUG4AprOBV2nSS/ukyD4 V8bg2/6cLS0GRKfDsqA3DcxSASWCAggIU4fTSj+DlYOZhNUIq14qzwqciZnO5CIH QDczSqu2LKRdP9j6MCtzIaZq/8pPDcOlgm7Dyct/kDo/64E2sg== =rD4j -----END PGP SIGNATURE----- Merge tag 'pull-loongarch-20230616' of https://gitlab.com/gaosong/qemu into staging pull-loongarch-20230616 # -----BEGIN PGP SIGNATURE----- # # iLMEAAEIAB0WIQS4/x2g0v3LLaCcbCxAov/yOSY+3wUCZIwysgAKCRBAov/yOSY+ # 39FYA/465KtY2jDt4xG6AdwZDHckfxZQWlrfhyZvtapOkUG4AprOBV2nSS/ukyD4 # V8bg2/6cLS0GRKfDsqA3DcxSASWCAggIU4fTSj+DlYOZhNUIq14qzwqciZnO5CIH # QDczSqu2LKRdP9j6MCtzIaZq/8pPDcOlgm7Dyct/kDo/64E2sg== # =rD4j # -----END PGP SIGNATURE----- # gpg: Signature made Fri 16 Jun 2023 12:00:18 PM CEST # gpg: using RSA key B8FF1DA0D2FDCB2DA09C6C2C40A2FFF239263EDF # gpg: Good signature from "Song Gao <m17746591750@163.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: B8FF 1DA0 D2FD CB2D A09C 6C2C 40A2 FFF2 3926 3EDF * tag 'pull-loongarch-20230616' of https://gitlab.com/gaosong/qemu: target/loongarch: Fix CSR.DMW0-3.VSEG check hw/loongarch: Supplement cpu topology arguments hw/loongarch: Add numa support hw/intc: Set physical cpuid route for LoongArch ipi device hw/loongarch/virt: Add cpu arch_id support Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
commit
e3660cc1e3
@ -17,6 +17,8 @@
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#include "target/loongarch/internals.h"
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#include "trace.h"
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static void loongarch_ipi_writel(void *, hwaddr, uint64_t, unsigned);
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static uint64_t loongarch_ipi_readl(void *opaque, hwaddr addr, unsigned size)
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{
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IPICore *s = opaque;
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@ -75,13 +77,42 @@ static void send_ipi_data(CPULoongArchState *env, uint64_t val, hwaddr addr)
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data, MEMTXATTRS_UNSPECIFIED, NULL);
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}
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static int archid_cmp(const void *a, const void *b)
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{
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CPUArchId *archid_a = (CPUArchId *)a;
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CPUArchId *archid_b = (CPUArchId *)b;
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return archid_a->arch_id - archid_b->arch_id;
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}
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static CPUArchId *find_cpu_by_archid(MachineState *ms, uint32_t id)
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{
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CPUArchId apic_id, *found_cpu;
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apic_id.arch_id = id;
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found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus,
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ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus),
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archid_cmp);
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return found_cpu;
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}
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static CPUState *ipi_getcpu(int arch_id)
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{
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MachineState *machine = MACHINE(qdev_get_machine());
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CPUArchId *archid;
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archid = find_cpu_by_archid(machine, arch_id);
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return CPU(archid->cpu);
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}
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static void ipi_send(uint64_t val)
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{
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uint32_t cpuid;
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uint8_t vector;
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CPULoongArchState *env;
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CPUState *cs;
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LoongArchCPU *cpu;
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LoongArchIPI *s;
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cpuid = extract32(val, 16, 10);
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if (cpuid >= LOONGARCH_MAX_CPUS) {
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@ -92,11 +123,10 @@ static void ipi_send(uint64_t val)
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/* IPI status vector */
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vector = extract8(val, 0, 5);
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cs = qemu_get_cpu(cpuid);
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cs = ipi_getcpu(cpuid);
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cpu = LOONGARCH_CPU(cs);
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env = &cpu->env;
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address_space_stl(&env->address_space_iocsr, 0x1008,
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BIT(vector), MEMTXATTRS_UNSPECIFIED, NULL);
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s = LOONGARCH_IPI(cpu->env.ipistate);
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loongarch_ipi_writel(&s->ipi_core, CORE_SET_OFF, BIT(vector), 4);
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}
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static void mail_send(uint64_t val)
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@ -114,7 +144,7 @@ static void mail_send(uint64_t val)
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}
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addr = 0x1020 + (val & 0x1c);
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cs = qemu_get_cpu(cpuid);
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cs = ipi_getcpu(cpuid);
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cpu = LOONGARCH_CPU(cs);
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env = &cpu->env;
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send_ipi_data(env, val, addr);
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@ -135,7 +165,7 @@ static void any_send(uint64_t val)
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}
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addr = val & 0xffff;
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cs = qemu_get_cpu(cpuid);
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cs = ipi_getcpu(cpuid);
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cpu = LOONGARCH_CPU(cs);
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env = &cpu->env;
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send_ipi_data(env, val, addr);
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@ -21,3 +21,4 @@ config LOONGARCH_VIRT
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select FW_CFG_DMA
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select DIMM
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select PFLASH_CFI01
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select ACPI_HMAT
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@ -34,6 +34,7 @@
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#include "sysemu/tpm.h"
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#include "hw/platform-bus.h"
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#include "hw/acpi/aml-build.h"
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#include "hw/acpi/hmat.h"
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#define ACPI_BUILD_ALIGN_SIZE 0x1000
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#define ACPI_BUILD_TABLE_SIZE 0x20000
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@ -107,7 +108,9 @@ static void
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build_madt(GArray *table_data, BIOSLinker *linker, LoongArchMachineState *lams)
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{
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MachineState *ms = MACHINE(lams);
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int i;
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MachineClass *mc = MACHINE_GET_CLASS(ms);
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const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms);
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int i, arch_id;
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AcpiTable table = { .sig = "APIC", .rev = 1, .oem_id = lams->oem_id,
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.oem_table_id = lams->oem_table_id };
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@ -117,13 +120,15 @@ build_madt(GArray *table_data, BIOSLinker *linker, LoongArchMachineState *lams)
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build_append_int_noprefix(table_data, 0, 4);
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build_append_int_noprefix(table_data, 1 /* PCAT_COMPAT */, 4); /* Flags */
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for (i = 0; i < ms->smp.cpus; i++) {
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for (i = 0; i < arch_ids->len; i++) {
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/* Processor Core Interrupt Controller Structure */
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arch_id = arch_ids->cpus[i].arch_id;
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build_append_int_noprefix(table_data, 17, 1); /* Type */
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build_append_int_noprefix(table_data, 15, 1); /* Length */
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build_append_int_noprefix(table_data, 1, 1); /* Version */
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build_append_int_noprefix(table_data, i + 1, 4); /* ACPI Processor ID */
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build_append_int_noprefix(table_data, i, 4); /* Core ID */
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build_append_int_noprefix(table_data, arch_id, 4); /* Core ID */
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build_append_int_noprefix(table_data, 1, 4); /* Flags */
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}
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@ -159,9 +164,12 @@ build_madt(GArray *table_data, BIOSLinker *linker, LoongArchMachineState *lams)
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static void
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build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
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{
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uint64_t i;
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int i, arch_id, node_id;
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uint64_t mem_len, mem_base;
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int nb_numa_nodes = machine->numa_state->num_nodes;
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LoongArchMachineState *lams = LOONGARCH_MACHINE(machine);
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MachineState *ms = MACHINE(lams);
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MachineClass *mc = MACHINE_GET_CLASS(lams);
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const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(machine);
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AcpiTable table = { .sig = "SRAT", .rev = 1, .oem_id = lams->oem_id,
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.oem_table_id = lams->oem_table_id };
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@ -169,13 +177,16 @@ build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
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build_append_int_noprefix(table_data, 1, 4); /* Reserved */
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build_append_int_noprefix(table_data, 0, 8); /* Reserved */
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for (i = 0; i < ms->smp.cpus; ++i) {
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for (i = 0; i < arch_ids->len; ++i) {
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arch_id = arch_ids->cpus[i].arch_id;
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node_id = arch_ids->cpus[i].props.node_id;
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/* Processor Local APIC/SAPIC Affinity Structure */
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build_append_int_noprefix(table_data, 0, 1); /* Type */
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build_append_int_noprefix(table_data, 16, 1); /* Length */
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/* Proximity Domain [7:0] */
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build_append_int_noprefix(table_data, 0, 1);
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build_append_int_noprefix(table_data, i, 1); /* APIC ID */
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build_append_int_noprefix(table_data, node_id, 1);
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build_append_int_noprefix(table_data, arch_id, 1); /* APIC ID */
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/* Flags, Table 5-36 */
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build_append_int_noprefix(table_data, 1, 4);
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build_append_int_noprefix(table_data, 0, 1); /* Local SAPIC EID */
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@ -184,16 +195,36 @@ build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
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build_append_int_noprefix(table_data, 0, 4); /* Reserved */
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}
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/* Node0 */
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build_srat_memory(table_data, VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE,
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0, MEM_AFFINITY_ENABLED);
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mem_base = VIRT_HIGHMEM_BASE;
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if (!nb_numa_nodes) {
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mem_len = machine->ram_size - VIRT_LOWMEM_SIZE;
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} else {
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mem_len = machine->numa_state->nodes[0].node_mem - VIRT_LOWMEM_SIZE;
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}
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if (mem_len)
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build_srat_memory(table_data, mem_base, mem_len, 0, MEM_AFFINITY_ENABLED);
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build_srat_memory(table_data, VIRT_HIGHMEM_BASE, machine->ram_size - VIRT_LOWMEM_SIZE,
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0, MEM_AFFINITY_ENABLED);
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/* Node1 - Nodemax */
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if (nb_numa_nodes) {
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mem_base += mem_len;
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for (i = 1; i < nb_numa_nodes; ++i) {
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if (machine->numa_state->nodes[i].node_mem > 0) {
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build_srat_memory(table_data, mem_base,
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machine->numa_state->nodes[i].node_mem, i,
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MEM_AFFINITY_ENABLED);
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mem_base += machine->numa_state->nodes[i].node_mem;
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}
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}
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}
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if (ms->device_memory) {
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build_srat_memory(table_data, ms->device_memory->base,
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memory_region_size(&ms->device_memory->mr),
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0, MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
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if (machine->device_memory) {
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build_srat_memory(table_data, machine->device_memory->base,
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memory_region_size(&machine->device_memory->mr),
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nb_numa_nodes - 1,
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MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
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}
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acpi_table_end(linker, &table);
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@ -406,9 +437,26 @@ static void acpi_build(AcpiBuildTables *tables, MachineState *machine)
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acpi_add_table(table_offsets, tables_blob);
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build_madt(tables_blob, tables->linker, lams);
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acpi_add_table(table_offsets, tables_blob);
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build_pptt(tables_blob, tables->linker, machine,
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lams->oem_id, lams->oem_table_id);
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acpi_add_table(table_offsets, tables_blob);
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build_srat(tables_blob, tables->linker, machine);
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if (machine->numa_state->num_nodes) {
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if (machine->numa_state->have_numa_distance) {
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acpi_add_table(table_offsets, tables_blob);
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build_slit(tables_blob, tables->linker, machine, lams->oem_id,
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lams->oem_table_id);
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}
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if (machine->numa_state->hmat_enabled) {
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acpi_add_table(table_offsets, tables_blob);
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build_hmat(tables_blob, tables->linker, machine->numa_state,
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lams->oem_id, lams->oem_table_id);
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}
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}
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acpi_add_table(table_offsets, tables_blob);
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{
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AcpiMcfgInfo mcfg = {
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@ -164,11 +164,16 @@ static void fdt_add_cpu_nodes(const LoongArchMachineState *lams)
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for (num = smp_cpus - 1; num >= 0; num--) {
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char *nodename = g_strdup_printf("/cpus/cpu@%d", num);
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LoongArchCPU *cpu = LOONGARCH_CPU(qemu_get_cpu(num));
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CPUState *cs = CPU(cpu);
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qemu_fdt_add_subnode(ms->fdt, nodename);
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qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu");
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qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
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cpu->dtb_compatible);
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if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) {
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qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id",
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ms->possible_cpus->cpus[cs->cpu_index].props.node_id);
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}
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qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", num);
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qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle",
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qemu_fdt_alloc_phandle(ms->fdt));
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@ -280,6 +285,22 @@ static void fdt_add_irqchip_node(LoongArchMachineState *lams)
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g_free(nodename);
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}
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static void fdt_add_memory_node(MachineState *ms,
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uint64_t base, uint64_t size, int node_id)
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{
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char *nodename = g_strdup_printf("/memory@%" PRIx64, base);
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qemu_fdt_add_subnode(ms->fdt, nodename);
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qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 2, base, 2, size);
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qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory");
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if (ms->numa_state && ms->numa_state->num_nodes) {
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qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", node_id);
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}
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g_free(nodename);
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}
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#define PM_BASE 0x10080000
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#define PM_SIZE 0x100
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#define PM_CTRL 0x10
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@ -617,6 +638,7 @@ static void loongarch_irq_init(LoongArchMachineState *lams)
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memory_region_add_subregion(&env->system_iocsr, APIC_BASE,
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sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi),
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cpu));
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env->ipistate = ipi;
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}
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/*
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@ -766,11 +788,17 @@ static void loongarch_init(MachineState *machine)
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const char *cpu_model = machine->cpu_type;
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ram_addr_t offset = 0;
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ram_addr_t ram_size = machine->ram_size;
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uint64_t highram_size = 0;
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uint64_t highram_size = 0, phyAddr = 0;
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MemoryRegion *address_space_mem = get_system_memory();
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LoongArchMachineState *lams = LOONGARCH_MACHINE(machine);
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int nb_numa_nodes = machine->numa_state->num_nodes;
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NodeInfo *numa_info = machine->numa_state->nodes;
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int i;
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hwaddr fdt_base;
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const CPUArchIdList *possible_cpus;
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MachineClass *mc = MACHINE_GET_CLASS(machine);
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CPUState *cpu;
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char *ramName = NULL;
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if (!cpu_model) {
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cpu_model = LOONGARCH_CPU_TYPE_NAME("la464");
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@ -787,21 +815,51 @@ static void loongarch_init(MachineState *machine)
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}
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create_fdt(lams);
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/* Init CPUs */
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for (i = 0; i < machine->smp.cpus; i++) {
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cpu_create(machine->cpu_type);
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possible_cpus = mc->possible_cpu_arch_ids(machine);
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for (i = 0; i < possible_cpus->len; i++) {
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cpu = cpu_create(machine->cpu_type);
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cpu->cpu_index = i;
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machine->possible_cpus->cpus[i].cpu = OBJECT(cpu);
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}
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fdt_add_cpu_nodes(lams);
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/* Add memory region */
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memory_region_init_alias(&lams->lowmem, NULL, "loongarch.lowram",
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machine->ram, 0, 256 * MiB);
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memory_region_add_subregion(address_space_mem, offset, &lams->lowmem);
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offset += 256 * MiB;
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memmap_add_entry(0, 256 * MiB, 1);
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highram_size = ram_size - 256 * MiB;
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memory_region_init_alias(&lams->highmem, NULL, "loongarch.highmem",
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machine->ram, offset, highram_size);
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memory_region_add_subregion(address_space_mem, 0x90000000, &lams->highmem);
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memmap_add_entry(0x90000000, highram_size, 1);
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/* Node0 memory */
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memmap_add_entry(VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, 1);
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fdt_add_memory_node(machine, VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, 0);
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memory_region_init_alias(&lams->lowmem, NULL, "loongarch.node0.lowram",
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machine->ram, offset, VIRT_LOWMEM_SIZE);
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memory_region_add_subregion(address_space_mem, phyAddr, &lams->lowmem);
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offset += VIRT_LOWMEM_SIZE;
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if (nb_numa_nodes > 0) {
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assert(numa_info[0].node_mem > VIRT_LOWMEM_SIZE);
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highram_size = numa_info[0].node_mem - VIRT_LOWMEM_SIZE;
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} else {
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highram_size = ram_size - VIRT_LOWMEM_SIZE;
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}
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phyAddr = VIRT_HIGHMEM_BASE;
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memmap_add_entry(phyAddr, highram_size, 1);
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fdt_add_memory_node(machine, phyAddr, highram_size, 0);
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memory_region_init_alias(&lams->highmem, NULL, "loongarch.node0.highram",
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||||
machine->ram, offset, highram_size);
|
||||
memory_region_add_subregion(address_space_mem, phyAddr, &lams->highmem);
|
||||
|
||||
/* Node1 - Nodemax memory */
|
||||
offset += highram_size;
|
||||
phyAddr += highram_size;
|
||||
|
||||
for (i = 1; i < nb_numa_nodes; i++) {
|
||||
MemoryRegion *nodemem = g_new(MemoryRegion, 1);
|
||||
ramName = g_strdup_printf("loongarch.node%d.ram", i);
|
||||
memory_region_init_alias(nodemem, NULL, ramName, machine->ram,
|
||||
offset, numa_info[i].node_mem);
|
||||
memory_region_add_subregion(address_space_mem, phyAddr, nodemem);
|
||||
memmap_add_entry(phyAddr, numa_info[i].node_mem, 1);
|
||||
fdt_add_memory_node(machine, phyAddr, numa_info[i].node_mem, i);
|
||||
offset += numa_info[i].node_mem;
|
||||
phyAddr += numa_info[i].node_mem;
|
||||
}
|
||||
|
||||
/* initialize device memory address space */
|
||||
if (machine->ram_size < machine->maxram_size) {
|
||||
@ -1022,6 +1080,58 @@ static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
|
||||
{
|
||||
int n;
|
||||
unsigned int max_cpus = ms->smp.max_cpus;
|
||||
|
||||
if (ms->possible_cpus) {
|
||||
assert(ms->possible_cpus->len == max_cpus);
|
||||
return ms->possible_cpus;
|
||||
}
|
||||
|
||||
ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
|
||||
sizeof(CPUArchId) * max_cpus);
|
||||
ms->possible_cpus->len = max_cpus;
|
||||
for (n = 0; n < ms->possible_cpus->len; n++) {
|
||||
ms->possible_cpus->cpus[n].type = ms->cpu_type;
|
||||
ms->possible_cpus->cpus[n].arch_id = n;
|
||||
|
||||
ms->possible_cpus->cpus[n].props.has_socket_id = true;
|
||||
ms->possible_cpus->cpus[n].props.socket_id =
|
||||
n / (ms->smp.cores * ms->smp.threads);
|
||||
ms->possible_cpus->cpus[n].props.has_core_id = true;
|
||||
ms->possible_cpus->cpus[n].props.core_id =
|
||||
n / ms->smp.threads % ms->smp.cores;
|
||||
ms->possible_cpus->cpus[n].props.has_thread_id = true;
|
||||
ms->possible_cpus->cpus[n].props.thread_id = n % ms->smp.threads;
|
||||
}
|
||||
return ms->possible_cpus;
|
||||
}
|
||||
|
||||
static CpuInstanceProperties
|
||||
virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
|
||||
{
|
||||
MachineClass *mc = MACHINE_GET_CLASS(ms);
|
||||
const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
|
||||
|
||||
assert(cpu_index < possible_cpus->len);
|
||||
return possible_cpus->cpus[cpu_index].props;
|
||||
}
|
||||
|
||||
static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx)
|
||||
{
|
||||
int64_t nidx = 0;
|
||||
|
||||
if (ms->numa_state->num_nodes) {
|
||||
nidx = idx / (ms->smp.cpus / ms->numa_state->num_nodes);
|
||||
if (ms->numa_state->num_nodes <= nidx) {
|
||||
nidx = ms->numa_state->num_nodes - 1;
|
||||
}
|
||||
}
|
||||
return nidx;
|
||||
}
|
||||
|
||||
static void loongarch_class_init(ObjectClass *oc, void *data)
|
||||
{
|
||||
MachineClass *mc = MACHINE_CLASS(oc);
|
||||
@ -1038,6 +1148,12 @@ static void loongarch_class_init(ObjectClass *oc, void *data)
|
||||
mc->block_default_type = IF_VIRTIO;
|
||||
mc->default_boot_order = "c";
|
||||
mc->no_cdrom = 1;
|
||||
mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;
|
||||
mc->cpu_index_to_instance_props = virt_cpu_index_to_props;
|
||||
mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
|
||||
mc->numa_mem_supported = true;
|
||||
mc->auto_enable_numa_with_memhp = true;
|
||||
mc->auto_enable_numa_with_memdev = true;
|
||||
mc->get_hotplug_handler = virt_machine_get_hotplug_handler;
|
||||
mc->default_nic = "virtio-net-pci";
|
||||
hc->plug = loongarch_machine_device_plug_cb;
|
||||
|
||||
@ -351,6 +351,8 @@ typedef struct CPUArchState {
|
||||
MemoryRegion iocsr_mem;
|
||||
bool load_elf;
|
||||
uint64_t elf_address;
|
||||
/* Store ipistate to access from this struct */
|
||||
DeviceState *ipistate;
|
||||
#endif
|
||||
} CPULoongArchState;
|
||||
|
||||
|
||||
@ -185,10 +185,10 @@ static int get_physical_address(CPULoongArchState *env, hwaddr *physical,
|
||||
}
|
||||
|
||||
plv = kernel_mode | (user_mode << R_CSR_DMW_PLV3_SHIFT);
|
||||
base_v = address >> TARGET_VIRT_ADDR_SPACE_BITS;
|
||||
base_v = address >> R_CSR_DMW_VSEG_SHIFT;
|
||||
/* Check direct map window */
|
||||
for (int i = 0; i < 4; i++) {
|
||||
base_c = env->CSR_DMW[i] >> TARGET_VIRT_ADDR_SPACE_BITS;
|
||||
base_c = FIELD_EX64(env->CSR_DMW[i], CSR_DMW, VSEG);
|
||||
if ((plv & env->CSR_DMW[i]) && (base_c == base_v)) {
|
||||
*physical = dmw_va2pa(address);
|
||||
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user