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target/xtensa: implement PREFCTL SR 

Cache prefetch option adds an unprivileged SR PREFCTL. Add trivial
implementation for this SR.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
This commit is contained in:
Max Filippov 2019-02-18 03:11:40 -08:00
parent 068e538a54
commit eb3f4298c9
2 changed files with 17 additions and 0 deletions
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1
target/xtensa/cpu.h
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@ -131,6 +131,7 @@ enum {
ACCLO = 16,
ACCHI = 17,
MR = 32,
PREFCTL = 40,
WINDOW_BASE = 72,
WINDOW_START = 73,
PTEVADDR = 83,

16
target/xtensa/translate.c
View File

@ -134,6 +134,7 @@ static const XtensaReg sregnames[256] = {
[MR + 1] = XTENSA_REG("MR1", XTENSA_OPTION_MAC16),
[MR + 2] = XTENSA_REG("MR2", XTENSA_OPTION_MAC16),
[MR + 3] = XTENSA_REG("MR3", XTENSA_OPTION_MAC16),
[PREFCTL] = XTENSA_REG_BITS("PREFCTL", XTENSA_OPTION_ALL),
[WINDOW_BASE] = XTENSA_REG("WINDOW_BASE", XTENSA_OPTION_WINDOWED_REGISTER),
[WINDOW_START] = XTENSA_REG("WINDOW_START",
XTENSA_OPTION_WINDOWED_REGISTER),
@ -4152,6 +4153,11 @@ static const XtensaOpcodeOps core_ops[] = {
.test_ill = test_ill_rsr,
.par = (const uint32_t[]){MISC + 3},
.op_flags = XTENSA_OP_PRIVILEGED,
}, {
.name = "rsr.prefctl",
.translate = translate_rsr,
.test_ill = test_ill_rsr,
.par = (const uint32_t[]){PREFCTL},
}, {
.name = "rsr.prid",
.translate = translate_rsr,
@ -4777,6 +4783,11 @@ static const XtensaOpcodeOps core_ops[] = {
.test_ill = test_ill_wsr,
.par = (const uint32_t[]){MMID},
.op_flags = XTENSA_OP_PRIVILEGED,
}, {
.name = "wsr.prefctl",
.translate = translate_wsr,
.test_ill = test_ill_wsr,
.par = (const uint32_t[]){PREFCTL},
}, {
.name = "wsr.prid",
.translate = translate_wsr,
@ -5265,6 +5276,11 @@ static const XtensaOpcodeOps core_ops[] = {
.test_ill = test_ill_xsr,
.par = (const uint32_t[]){MISC + 3},
.op_flags = XTENSA_OP_PRIVILEGED,
}, {
.name = "xsr.prefctl",
.translate = translate_xsr,
.test_ill = test_ill_xsr,
.par = (const uint32_t[]){PREFCTL},
}, {
.name = "xsr.prid",
.translate = translate_xsr,