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* Fix sign-extension for SMLAL* instructions

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* Various ptimer device conversions to new transaction API
  * Add a dummy Samsung SDHCI controller model to exynos4 boards
  * Minor refactorings of RAM creation for some arm boards
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Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20191022-2' into staging

 * Fix sign-extension for SMLAL* instructions
 * Various ptimer device conversions to new transaction API
 * Add a dummy Samsung SDHCI controller model to exynos4 boards
 * Minor refactorings of RAM creation for some arm boards

# gpg: Signature made Tue 22 Oct 2019 17:44:26 BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20191022-2:
  hw/arm/digic4: Inline digic4_board_setup_ram() function
  hw/arm/omap1: Create the RAM in the board
  hw/arm/omap2: Create the RAM in the board
  hw/arm/collie: Create the RAM in the board
  hw/arm/mps2: Use the IEC binary prefix definitions
  hw/arm/xilinx_zynq: Use the IEC binary prefix definitions
  hw/arm/exynos4210: Use the Samsung s3c SDHCI controller
  hw/sd/sdhci: Add dummy Samsung SDHCI controller
  hw/sd/sdhci: Add a comment to distinct the i.MX eSDHC functions
  hw/m68k/mcf5208.c: Switch to transaction-based ptimer API
  hw/watchdog/etraxfs_timer.c: Switch to transaction-based ptimer API
  hw/timer/altera_timer.c: Switch to transaction-based ptimer API
  hw/timer/lm32_timer: Switch to transaction-based ptimer API
  hw/timer/sh_timer: Switch to transaction-based ptimer API
  hw/timer/puv3_ost.c: Switch to transaction-based ptimer API
  hw/timer/arm_mptimer.c: Undo accidental rename of arm_mptimer_init()
  hw/timer/exynos4210_mct: Initialize ptimer before starting it
  target/arm: Fix sign-extension for SMLAL*

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2019-10-22 17:50:39 +01:00
commit ec97eb6133
25 changed files with 174 additions and 86 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
hw/arm/collie.c
View File

@ -27,9 +27,13 @@ static void collie_init(MachineState *machine)
{
StrongARMState *s;
DriveInfo *dinfo;
MemoryRegion *sysmem = get_system_memory();
MemoryRegion *sdram = g_new(MemoryRegion, 1);
s = sa1110_init(sysmem, collie_binfo.ram_size, machine->cpu_type);
s = sa1110_init(machine->cpu_type);
memory_region_allocate_system_memory(sdram, NULL, "strongarm.sdram",
collie_binfo.ram_size);
memory_region_add_subregion(get_system_memory(), SA_SDCS0, sdram);
dinfo = drive_get(IF_PFLASH, 0, 0);
pflash_cfi01_register(SA_CS0, "collie.fl1", 0x02000000,

9
hw/arm/digic_boards.c
View File

@ -53,12 +53,6 @@ typedef struct DigicBoard {
const char *rom1_def_filename;
} DigicBoard;
static void digic4_board_setup_ram(DigicBoardState *s, hwaddr ram_size)
{
memory_region_allocate_system_memory(&s->ram, NULL, "ram", ram_size);
memory_region_add_subregion(get_system_memory(), 0, &s->ram);
}
static void digic4_board_init(DigicBoard *board)
{
Error *err = NULL;
@ -72,7 +66,8 @@ static void digic4_board_init(DigicBoard *board)
exit(1);
}
digic4_board_setup_ram(s, board->ram_size);
memory_region_allocate_system_memory(&s->ram, NULL, "ram", board->ram_size);
memory_region_add_subregion(get_system_memory(), 0, &s->ram);
if (board->add_rom0) {
board->add_rom0(s, DIGIC4_ROM0_BASE, board->rom0_def_filename);

2
hw/arm/exynos4210.c
View File

@ -405,7 +405,7 @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
* public datasheet which is very similar (implementing
* MMC Specification Version 4.0 being the only difference noted)
*/
dev = qdev_create(NULL, TYPE_SYSBUS_SDHCI);
dev = qdev_create(NULL, TYPE_S3C_SDHCI);
qdev_prop_set_uint64(dev, "capareg", EXYNOS4210_SDHCI_CAPABILITIES);
qdev_init_nofail(dev);

3
hw/arm/mps2-tz.c
View File

@ -38,6 +38,7 @@
*/
#include "qemu/osdep.h"
#include "qemu/units.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "hw/arm/boot.h"
@ -458,7 +459,7 @@ static void mps2tz_common_init(MachineState *machine)
* call the 16MB our "system memory", as it's the largest lump.
*/
memory_region_allocate_system_memory(&mms->psram,
NULL, "mps.ram", 0x01000000);
NULL, "mps.ram", 16 * MiB);
memory_region_add_subregion(system_memory, 0x80000000, &mms->psram);
/* The overflow IRQs for all UARTs are ORed together.

3
hw/arm/mps2.c
View File

@ -23,6 +23,7 @@
*/
#include "qemu/osdep.h"
#include "qemu/units.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "hw/arm/boot.h"
@ -146,7 +147,7 @@ static void mps2_common_init(MachineState *machine)
* zbt_boot_ctrl is always zero).
*/
memory_region_allocate_system_memory(&mms->psram,
NULL, "mps.ram", 0x1000000);
NULL, "mps.ram", 16 * MiB);
memory_region_add_subregion(system_memory, 0x21000000, &mms->psram);
switch (mmc->fpga_type) {

10
hw/arm/nseries.c
View File

@ -47,6 +47,7 @@
/* Nokia N8x0 support */
struct n800_s {
MemoryRegion sdram;
struct omap_mpu_state_s *mpu;
struct rfbi_chip_s blizzard;
@ -1311,11 +1312,14 @@ static int n810_atag_setup(const struct arm_boot_info *info, void *p)
static void n8x0_init(MachineState *machine,
struct arm_boot_info *binfo, int model)
{
MemoryRegion *sysmem = get_system_memory();
struct n800_s *s = (struct n800_s *) g_malloc0(sizeof(*s));
int sdram_size = binfo->ram_size;
uint64_t sdram_size = binfo->ram_size;
s->mpu = omap2420_mpu_init(sysmem, sdram_size, machine->cpu_type);
memory_region_allocate_system_memory(&s->sdram, NULL, "omap2.dram",
sdram_size);
memory_region_add_subregion(get_system_memory(), OMAP2_Q2_BASE, &s->sdram);
s->mpu = omap2420_mpu_init(&s->sdram, machine->cpu_type);
/* Setup peripherals
*

12
hw/arm/omap1.c
View File

@ -23,6 +23,7 @@
#include "qapi/error.h"
#include "qemu-common.h"
#include "cpu.h"
#include "exec/address-spaces.h"
#include "hw/boards.h"
#include "hw/hw.h"
#include "hw/irq.h"
@ -3858,8 +3859,7 @@ static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s,
return range_covers_byte(0xe1010000, 0xe1020004 - 0xe1010000, addr);
}
struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
unsigned long sdram_size,
struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *dram,
const char *cpu_type)
{
int i;
@ -3867,11 +3867,12 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
qemu_irq dma_irqs[6];
DriveInfo *dinfo;
SysBusDevice *busdev;
MemoryRegion *system_memory = get_system_memory();
/* Core */
s->mpu_model = omap310;
s->cpu = ARM_CPU(cpu_create(cpu_type));
s->sdram_size = sdram_size;
s->sdram_size = memory_region_size(dram);
s->sram_size = OMAP15XX_SRAM_SIZE;
s->wakeup = qemu_allocate_irq(omap_mpu_wakeup, s, 0);
@ -3880,9 +3881,6 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
omap_clk_init(s);
/* Memory-mapped stuff */
memory_region_allocate_system_memory(&s->emiff_ram, NULL, "omap1.dram",
s->sdram_size);
memory_region_add_subregion(system_memory, OMAP_EMIFF_BASE, &s->emiff_ram);
memory_region_init_ram(&s->imif_ram, NULL, "omap1.sram", s->sram_size,
&error_fatal);
memory_region_add_subregion(system_memory, OMAP_IMIF_BASE, &s->imif_ram);
@ -3925,7 +3923,7 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
s->port[tipb_mpui].addr_valid = omap_validate_tipb_mpui_addr;
/* Register SDRAM and SRAM DMA ports for fast transfers. */
soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->emiff_ram),
soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(dram),
OMAP_EMIFF_BASE, s->sdram_size);
soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->imif_ram),
OMAP_IMIF_BASE, s->sram_size);

13
hw/arm/omap2.c
View File

@ -22,6 +22,7 @@
#include "qemu/error-report.h"
#include "qapi/error.h"
#include "cpu.h"
#include "exec/address-spaces.h"
#include "sysemu/blockdev.h"
#include "sysemu/qtest.h"
#include "sysemu/reset.h"
@ -2276,8 +2277,7 @@ static const struct dma_irq_map omap2_dma_irq_map[] = {
{ 0, OMAP_INT_24XX_SDMA_IRQ3 },
};
struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem,
unsigned long sdram_size,
struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sdram,
const char *cpu_type)
{
struct omap_mpu_state_s *s = g_new0(struct omap_mpu_state_s, 1);
@ -2286,11 +2286,11 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem,
int i;
SysBusDevice *busdev;
struct omap_target_agent_s *ta;
MemoryRegion *sysmem = get_system_memory();
/* Core */
s->mpu_model = omap2420;
s->cpu = ARM_CPU(cpu_create(cpu_type));
s->sdram_size = sdram_size;
s->sram_size = OMAP242X_SRAM_SIZE;
s->wakeup = qemu_allocate_irq(omap_mpu_wakeup, s, 0);
@ -2299,9 +2299,6 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem,
omap_clk_init(s);
/* Memory-mapped stuff */
memory_region_allocate_system_memory(&s->sdram, NULL, "omap2.dram",
s->sdram_size);
memory_region_add_subregion(sysmem, OMAP2_Q2_BASE, &s->sdram);
memory_region_init_ram(&s->sram, NULL, "omap2.sram", s->sram_size,
&error_fatal);
memory_region_add_subregion(sysmem, OMAP2_SRAM_BASE, &s->sram);
@ -2338,8 +2335,8 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem,
s->port->addr_valid = omap2_validate_addr;
/* Register SDRAM and SRAM ports for fast DMA transfers. */
soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->sdram),
OMAP2_Q2_BASE, s->sdram_size);
soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(sdram),
OMAP2_Q2_BASE, memory_region_size(sdram));
soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->sram),
OMAP2_SRAM_BASE, s->sram_size);

8
hw/arm/omap_sx1.c
View File

@ -103,6 +103,7 @@ static void sx1_init(MachineState *machine, const int version)
{
struct omap_mpu_state_s *mpu;
MemoryRegion *address_space = get_system_memory();
MemoryRegion *dram = g_new(MemoryRegion, 1);
MemoryRegion *flash = g_new(MemoryRegion, 1);
MemoryRegion *cs = g_new(MemoryRegion, 4);
static uint32_t cs0val = 0x00213090;
@ -118,8 +119,11 @@ static void sx1_init(MachineState *machine, const int version)
flash_size = flash2_size;
}
mpu = omap310_mpu_init(address_space, sx1_binfo.ram_size,
machine->cpu_type);
memory_region_allocate_system_memory(dram, NULL, "omap1.dram",
sx1_binfo.ram_size);
memory_region_add_subregion(address_space, OMAP_EMIFF_BASE, dram);
mpu = omap310_mpu_init(dram, machine->cpu_type);
/* External Flash (EMIFS) */
memory_region_init_ram(flash, NULL, "omap_sx1.flash0-0", flash_size,

8
hw/arm/palm.c
View File

@ -190,16 +190,20 @@ static void palmte_init(MachineState *machine)
MemoryRegion *address_space_mem = get_system_memory();
struct omap_mpu_state_s *mpu;
int flash_size = 0x00800000;
int sdram_size = palmte_binfo.ram_size;
static uint32_t cs0val = 0xffffffff;
static uint32_t cs1val = 0x0000e1a0;
static uint32_t cs2val = 0x0000e1a0;
static uint32_t cs3val = 0xe1a0e1a0;
int rom_size, rom_loaded = 0;
MemoryRegion *dram = g_new(MemoryRegion, 1);
MemoryRegion *flash = g_new(MemoryRegion, 1);
MemoryRegion *cs = g_new(MemoryRegion, 4);
mpu = omap310_mpu_init(address_space_mem, sdram_size, machine->cpu_type);
memory_region_allocate_system_memory(dram, NULL, "omap1.dram",
palmte_binfo.ram_size);
memory_region_add_subregion(address_space_mem, OMAP_EMIFF_BASE, dram);
mpu = omap310_mpu_init(dram, machine->cpu_type);
/* External Flash (EMIFS) */
memory_region_init_ram(flash, NULL, "palmte.flash", flash_size,

7
hw/arm/strongarm.c
View File

@ -1586,8 +1586,7 @@ static const TypeInfo strongarm_ssp_info = {
};
/* Main CPU functions */
StrongARMState *sa1110_init(MemoryRegion *sysmem,
unsigned int sdram_size, const char *cpu_type)
StrongARMState *sa1110_init(const char *cpu_type)
{
StrongARMState *s;
int i;
@ -1601,10 +1600,6 @@ StrongARMState *sa1110_init(MemoryRegion *sysmem,
s->cpu = ARM_CPU(cpu_create(cpu_type));
memory_region_allocate_system_memory(&s->sdram, NULL, "strongarm.sdram",
sdram_size);
memory_region_add_subregion(sysmem, SA_SDCS0, &s->sdram);
s->pic = sysbus_create_varargs("strongarm_pic", 0x90050000,
qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ),
qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ),

4
hw/arm/strongarm.h
View File

@ -55,7 +55,6 @@ enum {
typedef struct {
ARMCPU *cpu;
MemoryRegion sdram;
DeviceState *pic;
DeviceState *gpio;
DeviceState *ppc;
@ -63,7 +62,6 @@ typedef struct {
SSIBus *ssp_bus;
} StrongARMState;
StrongARMState *sa1110_init(MemoryRegion *sysmem,
unsigned int sdram_size, const char *rev);
StrongARMState *sa1110_init(const char *cpu_type);
#endif

3
hw/arm/xilinx_zynq.c
View File

@ -16,6 +16,7 @@
*/
#include "qemu/osdep.h"
#include "qemu/units.h"
#include "qapi/error.h"
#include "cpu.h"
#include "hw/sysbus.h"
@ -194,7 +195,7 @@ static void zynq_init(MachineState *machine)
memory_region_add_subregion(address_space_mem, 0, ext_ram);
/* 256K of on-chip memory */
memory_region_init_ram(ocm_ram, NULL, "zynq.ocm_ram", 256 << 10,
memory_region_init_ram(ocm_ram, NULL, "zynq.ocm_ram", 256 * KiB,
&error_fatal);
memory_region_add_subregion(address_space_mem, 0xFFFC0000, ocm_ram);

9
hw/m68k/mcf5208.c
View File

@ -9,7 +9,6 @@
#include "qemu/osdep.h"
#include "qemu/units.h"
#include "qemu/error-report.h"
#include "qemu/main-loop.h"
#include "qapi/error.h"
#include "qemu-common.h"
#include "cpu.h"
@ -79,6 +78,7 @@ static void m5208_timer_write(void *opaque, hwaddr offset,
return;
}
ptimer_transaction_begin(s->timer);
if (s->pcsr & PCSR_EN)
ptimer_stop(s->timer);
@ -94,8 +94,10 @@ static void m5208_timer_write(void *opaque, hwaddr offset,
if (s->pcsr & PCSR_EN)
ptimer_run(s->timer, 0);
ptimer_transaction_commit(s->timer);
break;
case 2:
ptimer_transaction_begin(s->timer);
s->pmr = value;
s->pcsr &= ~PCSR_PIF;
if ((s->pcsr & PCSR_RLD) == 0) {
@ -104,6 +106,7 @@ static void m5208_timer_write(void *opaque, hwaddr offset,
} else {
ptimer_set_limit(s->timer, value, s->pcsr & PCSR_OVW);
}
ptimer_transaction_commit(s->timer);
break;
case 4:
break;
@ -182,7 +185,6 @@ static void mcf5208_sys_init(MemoryRegion *address_space, qemu_irq *pic)
{
MemoryRegion *iomem = g_new(MemoryRegion, 1);
m5208_timer_state *s;
QEMUBH *bh;
int i;
/* SDRAMC. */
@ -191,8 +193,7 @@ static void mcf5208_sys_init(MemoryRegion *address_space, qemu_irq *pic)
/* Timers. */
for (i = 0; i < 2; i++) {
s = g_new0(m5208_timer_state, 1);
bh = qemu_bh_new(m5208_timer_trigger, s);
s->timer = ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT);
s->timer = ptimer_init(m5208_timer_trigger, s, PTIMER_POLICY_DEFAULT);
memory_region_init_io(&s->iomem, NULL, &m5208_timer_ops, s,
"m5208-timer", 0x00004000);
memory_region_add_subregion(address_space, 0xfc080000 + 0x4000 * i,

68
hw/sd/sdhci.c
View File

@ -1532,6 +1532,8 @@ static const TypeInfo sdhci_bus_info = {
.class_init = sdhci_bus_class_init,
};
/* --- qdev i.MX eSDHC --- */
static uint64_t usdhc_read(void *opaque, hwaddr offset, unsigned size)
{
SDHCIState *s = SYSBUS_SDHCI(opaque);
@ -1734,7 +1736,6 @@ usdhc_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
}
}
static const MemoryRegionOps usdhc_mmio_ops = {
.read = usdhc_read,
.write = usdhc_write,
@ -1760,11 +1761,76 @@ static const TypeInfo imx_usdhc_info = {
.instance_init = imx_usdhc_init,
};
/* --- qdev Samsung s3c --- */
#define S3C_SDHCI_CONTROL2 0x80
#define S3C_SDHCI_CONTROL3 0x84
#define S3C_SDHCI_CONTROL4 0x8c
static uint64_t sdhci_s3c_read(void *opaque, hwaddr offset, unsigned size)
{
uint64_t ret;
switch (offset) {
case S3C_SDHCI_CONTROL2:
case S3C_SDHCI_CONTROL3:
case S3C_SDHCI_CONTROL4:
/* ignore */
ret = 0;
break;
default:
ret = sdhci_read(opaque, offset, size);
break;
}
return ret;
}
static void sdhci_s3c_write(void *opaque, hwaddr offset, uint64_t val,
unsigned size)
{
switch (offset) {
case S3C_SDHCI_CONTROL2:
case S3C_SDHCI_CONTROL3:
case S3C_SDHCI_CONTROL4:
/* ignore */
break;
default:
sdhci_write(opaque, offset, val, size);
break;
}
}
static const MemoryRegionOps sdhci_s3c_mmio_ops = {
.read = sdhci_s3c_read,
.write = sdhci_s3c_write,
.valid = {
.min_access_size = 1,
.max_access_size = 4,
.unaligned = false
},
.endianness = DEVICE_LITTLE_ENDIAN,
};
static void sdhci_s3c_init(Object *obj)
{
SDHCIState *s = SYSBUS_SDHCI(obj);
s->io_ops = &sdhci_s3c_mmio_ops;
}
static const TypeInfo sdhci_s3c_info = {
.name = TYPE_S3C_SDHCI ,
.parent = TYPE_SYSBUS_SDHCI,
.instance_init = sdhci_s3c_init,
};
static void sdhci_register_types(void)
{
type_register_static(&sdhci_sysbus_info);
type_register_static(&sdhci_bus_info);
type_register_static(&imx_usdhc_info);
type_register_static(&sdhci_s3c_info);
}
type_init(sdhci_register_types)

13
hw/timer/altera_timer.c
View File

@ -19,7 +19,6 @@
*/
#include "qemu/osdep.h"
#include "qemu/main-loop.h"
#include "qemu/module.h"
#include "qapi/error.h"
@ -53,7 +52,6 @@ typedef struct AlteraTimer {
MemoryRegion mmio;
qemu_irq irq;
uint32_t freq_hz;
QEMUBH *bh;
ptimer_state *ptimer;
uint32_t regs[R_MAX];
} AlteraTimer;
@ -105,6 +103,7 @@ static void timer_write(void *opaque, hwaddr addr,
break;
case R_CONTROL:
ptimer_transaction_begin(t->ptimer);
t->regs[R_CONTROL] = value & (CONTROL_ITO | CONTROL_CONT);
if ((value & CONTROL_START) &&
!(t->regs[R_STATUS] & STATUS_RUN)) {
@ -115,10 +114,12 @@ static void timer_write(void *opaque, hwaddr addr,
ptimer_stop(t->ptimer);
t->regs[R_STATUS] &= ~STATUS_RUN;
}
ptimer_transaction_commit(t->ptimer);
break;
case R_PERIODL:
case R_PERIODH:
ptimer_transaction_begin(t->ptimer);
t->regs[addr] = value & 0xFFFF;
if (t->regs[R_STATUS] & STATUS_RUN) {
ptimer_stop(t->ptimer);
@ -126,6 +127,7 @@ static void timer_write(void *opaque, hwaddr addr,
}
tvalue = (t->regs[R_PERIODH] << 16) | t->regs[R_PERIODL];
ptimer_set_limit(t->ptimer, tvalue + 1, 1);
ptimer_transaction_commit(t->ptimer);
break;
case R_SNAPL:
@ -183,9 +185,10 @@ static void altera_timer_realize(DeviceState *dev, Error **errp)
return;
}
t->bh = qemu_bh_new(timer_hit, t);
t->ptimer = ptimer_init_with_bh(t->bh, PTIMER_POLICY_DEFAULT);
t->ptimer = ptimer_init(timer_hit, t, PTIMER_POLICY_DEFAULT);
ptimer_transaction_begin(t->ptimer);
ptimer_set_freq(t->ptimer, t->freq_hz);
ptimer_transaction_commit(t->ptimer);
memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t,
TYPE_ALTERA_TIMER, R_MAX * sizeof(uint32_t));
@ -204,8 +207,10 @@ static void altera_timer_reset(DeviceState *dev)
{
AlteraTimer *t = ALTERA_TIMER(dev);
ptimer_transaction_begin(t->ptimer);
ptimer_stop(t->ptimer);
ptimer_set_limit(t->ptimer, 0xffffffff, 1);
ptimer_transaction_commit(t->ptimer);
memset(t->regs, 0, sizeof(t->regs));
}

4
hw/timer/arm_mptimer.c
View File

@ -237,7 +237,7 @@ static void arm_mptimer_reset(DeviceState *dev)
}
}
static void arm_mptimer_init_with_bh(Object *obj)
static void arm_mptimer_init(Object *obj)
{
ARMMPTimerState *s = ARM_MPTIMER(obj);
@ -319,7 +319,7 @@ static const TypeInfo arm_mptimer_info = {
.name = TYPE_ARM_MPTIMER,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(ARMMPTimerState),
.instance_init = arm_mptimer_init_with_bh,
.instance_init = arm_mptimer_init,
.class_init = arm_mptimer_class_init,
};

23
hw/timer/etraxfs_timer.c
View File

@ -26,7 +26,6 @@
#include "hw/sysbus.h"
#include "sysemu/reset.h"
#include "sysemu/runstate.h"
#include "qemu/main-loop.h"
#include "qemu/module.h"
#include "qemu/timer.h"
#include "hw/irq.h"
@ -59,9 +58,6 @@ typedef struct ETRAXTimerState {
qemu_irq irq;
qemu_irq nmi;
QEMUBH *bh_t0;
QEMUBH *bh_t1;
QEMUBH *bh_wd;
ptimer_state *ptimer_t0;
ptimer_state *ptimer_t1;
ptimer_state *ptimer_wd;
@ -155,6 +151,7 @@ static void update_ctrl(ETRAXTimerState *t, int tnum)
}
D(printf ("freq_hz=%d div=%d\n", freq_hz, div));
ptimer_transaction_begin(timer);
ptimer_set_freq(timer, freq_hz);
ptimer_set_limit(timer, div, 0);
@ -176,6 +173,7 @@ static void update_ctrl(ETRAXTimerState *t, int tnum)
abort();
break;
}
ptimer_transaction_commit(timer);
}
static void timer_update_irq(ETRAXTimerState *t)
@ -240,6 +238,7 @@ static inline void timer_watchdog_update(ETRAXTimerState *t, uint32_t value)
t->wd_hits = 0;
ptimer_transaction_begin(t->ptimer_wd);
ptimer_set_freq(t->ptimer_wd, 760);
if (wd_cnt == 0)
wd_cnt = 256;
@ -250,6 +249,7 @@ static inline void timer_watchdog_update(ETRAXTimerState *t, uint32_t value)
ptimer_stop(t->ptimer_wd);
t->rw_wd_ctrl = value;
ptimer_transaction_commit(t->ptimer_wd);
}
static void
@ -311,9 +311,15 @@ static void etraxfs_timer_reset(void *opaque)
{
ETRAXTimerState *t = opaque;
ptimer_transaction_begin(t->ptimer_t0);
ptimer_stop(t->ptimer_t0);
ptimer_transaction_commit(t->ptimer_t0);
ptimer_transaction_begin(t->ptimer_t1);
ptimer_stop(t->ptimer_t1);
ptimer_transaction_commit(t->ptimer_t1);
ptimer_transaction_begin(t->ptimer_wd);
ptimer_stop(t->ptimer_wd);
ptimer_transaction_commit(t->ptimer_wd);
t->rw_wd_ctrl = 0;
t->r_intr = 0;
t->rw_intr_mask = 0;
@ -325,12 +331,9 @@ static void etraxfs_timer_realize(DeviceState *dev, Error **errp)
ETRAXTimerState *t = ETRAX_TIMER(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
t->bh_t0 = qemu_bh_new(timer0_hit, t);
t->bh_t1 = qemu_bh_new(timer1_hit, t);
t->bh_wd = qemu_bh_new(watchdog_hit, t);
t->ptimer_t0 = ptimer_init_with_bh(t->bh_t0, PTIMER_POLICY_DEFAULT);
t->ptimer_t1 = ptimer_init_with_bh(t->bh_t1, PTIMER_POLICY_DEFAULT);
t->ptimer_wd = ptimer_init_with_bh(t->bh_wd, PTIMER_POLICY_DEFAULT);
t->ptimer_t0 = ptimer_init(timer0_hit, t, PTIMER_POLICY_DEFAULT);
t->ptimer_t1 = ptimer_init(timer1_hit, t, PTIMER_POLICY_DEFAULT);
t->ptimer_wd = ptimer_init(watchdog_hit, t, PTIMER_POLICY_DEFAULT);
sysbus_init_irq(sbd, &t->irq);
sysbus_init_irq(sbd, &t->nmi);

2
hw/timer/exynos4210_mct.c
View File

@ -1254,7 +1254,7 @@ static void exynos4210_mct_write(void *opaque, hwaddr offset,
/* Start FRC if transition from disabled to enabled */
if ((value & G_TCON_TIMER_ENABLE) > (old_val &
G_TCON_TIMER_ENABLE)) {
exynos4210_gfrc_start(&s->g_timer);
exynos4210_gfrc_restart(s);
}
if ((value & G_TCON_TIMER_ENABLE) < (old_val &
G_TCON_TIMER_ENABLE)) {

13
hw/timer/lm32_timer.c
View File

@ -30,7 +30,6 @@
#include "hw/ptimer.h"
#include "hw/qdev-properties.h"
#include "qemu/error-report.h"
#include "qemu/main-loop.h"
#include "qemu/module.h"
#define DEFAULT_FREQUENCY (50*1000000)
@ -63,7 +62,6 @@ struct LM32TimerState {
MemoryRegion iomem;
QEMUBH *bh;
ptimer_state *ptimer;
qemu_irq irq;
@ -119,6 +117,7 @@ static void timer_write(void *opaque, hwaddr addr,
s->regs[R_SR] &= ~SR_TO;
break;
case R_CR:
ptimer_transaction_begin(s->ptimer);
s->regs[R_CR] = value;
if (s->regs[R_CR] & CR_START) {
ptimer_run(s->ptimer, 1);
@ -126,10 +125,13 @@ static void timer_write(void *opaque, hwaddr addr,
if (s->regs[R_CR] & CR_STOP) {
ptimer_stop(s->ptimer);
}
ptimer_transaction_commit(s->ptimer);
break;
case R_PERIOD:
s->regs[R_PERIOD] = value;
ptimer_transaction_begin(s->ptimer);
ptimer_set_count(s->ptimer, value);
ptimer_transaction_commit(s->ptimer);
break;
case R_SNAPSHOT:
error_report("lm32_timer: write access to read only register 0x"
@ -176,7 +178,9 @@ static void timer_reset(DeviceState *d)
for (i = 0; i < R_MAX; i++) {
s->regs[i] = 0;
}
ptimer_transaction_begin(s->ptimer);
ptimer_stop(s->ptimer);
ptimer_transaction_commit(s->ptimer);
}
static void lm32_timer_init(Object *obj)
@ -195,10 +199,11 @@ static void lm32_timer_realize(DeviceState *dev, Error **errp)
{
LM32TimerState *s = LM32_TIMER(dev);
s->bh = qemu_bh_new(timer_hit, s);
s->ptimer = ptimer_init_with_bh(s->bh, PTIMER_POLICY_DEFAULT);
s->ptimer = ptimer_init(timer_hit, s, PTIMER_POLICY_DEFAULT);
ptimer_transaction_begin(s->ptimer);
ptimer_set_freq(s->ptimer, s->freq_hz);
ptimer_transaction_commit(s->ptimer);
}
static const VMStateDescription vmstate_lm32_timer = {

9
hw/timer/puv3_ost.c
View File

@ -13,7 +13,6 @@
#include "hw/sysbus.h"
#include "hw/irq.h"
#include "hw/ptimer.h"
#include "qemu/main-loop.h"
#include "qemu/module.h"
#undef DEBUG_PUV3
@ -27,7 +26,6 @@ typedef struct PUV3OSTState {
SysBusDevice parent_obj;
MemoryRegion iomem;
QEMUBH *bh;
qemu_irq irq;
ptimer_state *ptimer;
@ -68,6 +66,7 @@ static void puv3_ost_write(void *opaque, hwaddr offset,
DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
switch (offset) {
case 0x00: /* Match Register 0 */
ptimer_transaction_begin(s->ptimer);
s->reg_OSMR0 = value;
if (s->reg_OSMR0 > s->reg_OSCR) {
ptimer_set_count(s->ptimer, s->reg_OSMR0 - s->reg_OSCR);
@ -76,6 +75,7 @@ static void puv3_ost_write(void *opaque, hwaddr offset,
(0xffffffff - s->reg_OSCR));
}
ptimer_run(s->ptimer, 2);
ptimer_transaction_commit(s->ptimer);
break;
case 0x14: /* Status Register */
assert(value == 0);
@ -128,9 +128,10 @@ static void puv3_ost_realize(DeviceState *dev, Error **errp)
sysbus_init_irq(sbd, &s->irq);
s->bh = qemu_bh_new(puv3_ost_tick, s);
s->ptimer = ptimer_init_with_bh(s->bh, PTIMER_POLICY_DEFAULT);
s->ptimer = ptimer_init(puv3_ost_tick, s, PTIMER_POLICY_DEFAULT);
ptimer_transaction_begin(s->ptimer);
ptimer_set_freq(s->ptimer, 50 * 1000 * 1000);
ptimer_transaction_commit(s->ptimer);
memory_region_init_io(&s->iomem, OBJECT(s), &puv3_ost_ops, s, "puv3_ost",
PUV3_REGS_OFFSET);

13
hw/timer/sh_timer.c
View File

@ -13,7 +13,6 @@
#include "hw/irq.h"
#include "hw/sh4/sh.h"
#include "qemu/timer.h"
#include "qemu/main-loop.h"
#include "hw/ptimer.h"
//#define DEBUG_TIMER
@ -91,13 +90,18 @@ static void sh_timer_write(void *opaque, hwaddr offset,
switch (offset >> 2) {
case OFFSET_TCOR:
s->tcor = value;
ptimer_transaction_begin(s->timer);
ptimer_set_limit(s->timer, s->tcor, 0);
ptimer_transaction_commit(s->timer);
break;
case OFFSET_TCNT:
s->tcnt = value;
ptimer_transaction_begin(s->timer);
ptimer_set_count(s->timer, s->tcnt);
ptimer_transaction_commit(s->timer);
break;
case OFFSET_TCR:
ptimer_transaction_begin(s->timer);
if (s->enabled) {
/* Pause the timer if it is running. This may cause some
inaccuracy dure to rounding, but avoids a whole lot of other
@ -148,6 +152,7 @@ static void sh_timer_write(void *opaque, hwaddr offset,
/* Restart the timer if still enabled. */
ptimer_run(s->timer, 0);
}
ptimer_transaction_commit(s->timer);
break;
case OFFSET_TCPR:
if (s->feat & TIMER_FEAT_CAPT) {
@ -168,12 +173,14 @@ static void sh_timer_start_stop(void *opaque, int enable)
printf("sh_timer_start_stop %d (%d)\n", enable, s->enabled);
#endif
ptimer_transaction_begin(s->timer);
if (s->enabled && !enable) {
ptimer_stop(s->timer);
}
if (!s->enabled && enable) {
ptimer_run(s->timer, 0);
}
ptimer_transaction_commit(s->timer);
s->enabled = !!enable;
#ifdef DEBUG_TIMER
@ -191,7 +198,6 @@ static void sh_timer_tick(void *opaque)
static void *sh_timer_init(uint32_t freq, int feat, qemu_irq irq)
{
sh_timer_state *s;
QEMUBH *bh;
s = (sh_timer_state *)g_malloc0(sizeof(sh_timer_state));
s->freq = freq;
@ -203,8 +209,7 @@ static void *sh_timer_init(uint32_t freq, int feat, qemu_irq irq)
s->enabled = 0;
s->irq = irq;
bh = qemu_bh_new(sh_timer_tick, s);
s->timer = ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT);
s->timer = ptimer_init(sh_timer_tick, s, PTIMER_POLICY_DEFAULT);
sh_timer_write(s, OFFSET_TCOR >> 2, s->tcor);
sh_timer_write(s, OFFSET_TCNT >> 2, s->tcnt);

10
include/hw/arm/omap.h
View File

@ -823,8 +823,6 @@ struct omap_mpu_state_s {
MemoryRegion mpui_io_iomem;
MemoryRegion tap_iomem;
MemoryRegion imif_ram;
MemoryRegion emiff_ram;
MemoryRegion sdram;
MemoryRegion sram;
struct omap_dma_port_if_s {
@ -836,7 +834,7 @@ struct omap_mpu_state_s {
hwaddr addr);
} port[__omap_dma_port_last];
unsigned long sdram_size;
uint64_t sdram_size;
unsigned long sram_size;
/* MPUI-TIPB peripherals */
@ -933,13 +931,11 @@ struct omap_mpu_state_s {
};
/* omap1.c */
struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
unsigned long sdram_size,
struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *sdram,
const char *core);
/* omap2.c */
struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem,
unsigned long sdram_size,
struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sdram,
const char *core);
uint32_t omap_badwidth_read8(void *opaque, hwaddr addr);

2
include/hw/sd/sdhci.h
View File

@ -116,4 +116,6 @@ typedef struct SDHCIState {
#define TYPE_IMX_USDHC "imx-usdhc"
#define TYPE_S3C_SDHCI "s3c-sdhci"
#endif /* SDHCI_H */

4
target/arm/translate.c
View File

@ -8045,7 +8045,9 @@ static bool op_smlaxxx(DisasContext *s, arg_rrrr *a,
case 2:
tl = load_reg(s, a->ra);
th = load_reg(s, a->rd);
t1 = tcg_const_i32(0);
/* Sign-extend the 32-bit product to 64 bits. */
t1 = tcg_temp_new_i32();
tcg_gen_sari_i32(t1, t0, 31);
tcg_gen_add2_i32(tl, th, tl, th, t0, t1);
tcg_temp_free_i32(t0);
tcg_temp_free_i32(t1);