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For consistency, align the address to the cache line before using it,

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when invalidating the instruction cache.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3449 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
j_mayer 2007-10-26 00:55:17 +00:00
parent dac454af57
commit f0685f6e7a
1 changed files with 2 additions and 2 deletions
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4
target-ppc/op_helper_mem.h
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@ -252,8 +252,8 @@ void glue(do_icbi, MEMSUFFIX) (void)
* (not a fetch) by the MMU. To be sure it will be so,
* do the load "by hand".
*/
tmp = glue(ldl, MEMSUFFIX)((uint32_t)T0);
T0 &= ~(env->icache_line_size - 1);
tmp = glue(ldl, MEMSUFFIX)((uint32_t)T0);
tb_invalidate_page_range((uint32_t)T0,
(uint32_t)(T0 + env->icache_line_size));
}
@ -267,8 +267,8 @@ void glue(do_icbi_64, MEMSUFFIX) (void)
* (not a fetch) by the MMU. To be sure it will be so,
* do the load "by hand".
*/
tmp = glue(ldq, MEMSUFFIX)((uint64_t)T0);
T0 &= ~(env->icache_line_size - 1);
tmp = glue(ldq, MEMSUFFIX)((uint64_t)T0);
tb_invalidate_page_range((uint64_t)T0,
(uint64_t)(T0 + env->icache_line_size));
}