OpenE2K/qemu-e2k
13
4
Fork 0
Code Issues 4 Pull Requests Projects 2 Releases Activity

disas/riscv: Add support for XVentanaCondOps

Browse Source 
This patch adds XVentanaCondOps support to the RISC-V disassembler.

Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230612111034.3955227-8-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Christoph Müllner 2023-06-12 13:10:33 +02:00 committed by Alistair Francis
parent c859a2424d
commit f6f72338d8
4 changed files with 67 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
disas/meson.build
View File

@ -6,7 +6,10 @@ common_ss.add(when: 'CONFIG_M68K_DIS', if_true: files('m68k.c'))
common_ss.add(when: 'CONFIG_MICROBLAZE_DIS', if_true: files('microblaze.c'))
common_ss.add(when: 'CONFIG_MIPS_DIS', if_true: files('mips.c', 'nanomips.c'))
common_ss.add(when: 'CONFIG_NIOS2_DIS', if_true: files('nios2.c'))
common_ss.add(when: 'CONFIG_RISCV_DIS', if_true: files('riscv.c'))
common_ss.add(when: 'CONFIG_RISCV_DIS', if_true: files(
'riscv.c',
'riscv-xventana.c'
))
common_ss.add(when: 'CONFIG_SH4_DIS', if_true: files('sh4.c'))
common_ss.add(when: 'CONFIG_SPARC_DIS', if_true: files('sparc.c'))
common_ss.add(when: 'CONFIG_XTENSA_DIS', if_true: files('xtensa.c'))

41
disas/riscv-xventana.c Normal file
View File

@ -0,0 +1,41 @@
/*
* QEMU RISC-V Disassembler for xventana.
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#include "disas/riscv.h"
#include "disas/riscv-xventana.h"
typedef enum {
/* 0 is reserved for rv_op_illegal. */
ventana_op_vt_maskc = 1,
ventana_op_vt_maskcn = 2,
} rv_ventana_op;
const rv_opcode_data ventana_opcode_data[] = {
{ "vt.illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 },
{ "vt.maskc", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "vt.maskcn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
};
void decode_xventanacondops(rv_decode *dec, rv_isa isa)
{
rv_inst inst = dec->inst;
rv_opcode op = rv_op_illegal;
switch (((inst >> 0) & 0b11)) {
case 3:
switch (((inst >> 2) & 0b11111)) {
case 30:
switch (((inst >> 22) & 0b1111111000) | ((inst >> 12) & 0b0000000111)) {
case 6: op = ventana_op_vt_maskc; break;
case 7: op = ventana_op_vt_maskcn; break;
}
break;
}
break;
}
dec->op = op;
}

18
disas/riscv-xventana.h Normal file
View File

@ -0,0 +1,18 @@
/*
* QEMU disassembler -- RISC-V specific header (xventana*).
*
* Copyright (c) 2023 VRULL GmbH
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#ifndef DISAS_RISCV_XVENTANA_H
#define DISAS_RISCV_XVENTANA_H
#include "disas/riscv.h"
extern const rv_opcode_data ventana_opcode_data[];
void decode_xventanacondops(rv_decode*, rv_isa);
#endif /* DISAS_RISCV_XVENTANA_H */

4
disas/riscv.c
View File

@ -22,6 +22,9 @@
#include "target/riscv/cpu_cfg.h"
#include "disas/riscv.h"
/* Vendor extensions */
#include "disas/riscv-xventana.h"
typedef enum {
/* 0 is reserved for rv_op_illegal. */
rv_op_lui = 1,
@ -4708,6 +4711,7 @@ disasm_inst(char *buf, size_t buflen, rv_isa isa, uint64_t pc, rv_inst inst,
void (*decode_func)(rv_decode *, rv_isa);
} decoders[] = {
{ always_true_p, rvi_opcode_data, decode_inst_opcode },
{ has_XVentanaCondOps_p, ventana_opcode_data, decode_xventanacondops },
};
for (size_t i = 0; i < ARRAY_SIZE(decoders); i++) {