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tests/tcg/tricore: Add test for OPC2_32_RCRW_INSERT

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DREG_RS2 and DREG_CALC_RESULT were mapped to the same register which
would not trigger https://gitlab.com/qemu-project/qemu/-/issues/653. So
let's make each register unique.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20230202120432.1268-5-kbastian@mail.uni-paderborn.de>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
This commit is contained in:
Bastian Koppelmann 2023-02-02 13:04:26 +01:00
parent 1c6b2e4b79
commit fa581531ff
3 changed files with 22 additions and 4 deletions
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1
tests/tcg/tricore/Makefile.softmmu-target
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@ -11,6 +11,7 @@ TESTS += test_fadd.tst
TESTS += test_fmul.tst
TESTS += test_ftoi.tst
TESTS += test_imask.tst
TESTS += test_insert.tst
TESTS += test_madd.tst
TESTS += test_msub.tst
TESTS += test_muls.tst

16
tests/tcg/tricore/macros.h
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@ -9,10 +9,10 @@
/* Register definitions */
#define DREG_RS1 %d0
#define DREG_RS2 %d1
#define DREG_RS3 %d4
#define DREG_CALC_RESULT %d1
#define DREG_CALC_PSW %d2
#define DREG_CORRECT_PSW %d3
#define DREG_RS3 %d2
#define DREG_CALC_RESULT %d3
#define DREG_CALC_PSW %d4
#define DREG_CORRECT_PSW %d5
#define DREG_TEMP_LI %d10
#define DREG_TEMP %d11
#define DREG_TEST_NUM %d14
@ -103,6 +103,14 @@ test_ ## num: \
insn DREG_CALC_RESULT, DREG_RS1, DREG_RS2, imm; \
)
#define TEST_D_DIDI(insn, num, result, rs1, imm1, rs2, imm2) \
TEST_CASE(num, DREG_CALC_RESULT, result, \
LI(DREG_RS1, rs1); \
LI(DREG_RS2, rs1); \
rstv; \
insn DREG_CALC_RESULT, DREG_RS1, imm1, DREG_RS2, imm2; \
)
#define TEST_E_ED(insn, num, res_hi, res_lo, rs1_hi, rs1_lo, rs2) \
TEST_CASE_E(num, res_lo, res_hi, \
LI(EREG_RS1_LO, rs1_lo); \

9
tests/tcg/tricore/test_insert.S Normal file
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@ -0,0 +1,9 @@
#include "macros.h"
.text
.global _start
_start:
# insn num result rs1 imm1 rs2 imm2
# | | | | | | |
TEST_D_DIDI(insert, 1, 0x7fffffff, 0xffffffff, 0xa, 0x10, 0x8)
TEST_PASSFAIL