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hexagon: GETPC() fixes, shadowing fixes

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Merge tag 'pull-hex-20231018' of https://github.com/quic/qemu into staging

hexagon: GETPC() fixes, shadowing fixes

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# gpg: Signature made Thu 19 Oct 2023 11:01:58 JST
# gpg:                using RSA key 3D66AAE474594824C88CE0F81A54AFB8E5646C32
# gpg: Good signature from "Brian Cain <bcain@kernel.org>" [unknown]
# gpg:                 aka "Brian Cain (QuIC) <bcain@quicinc.com>" [unknown]
# gpg:                 aka "Brian Cain (CAF) <bcain@codeaurora.org>" [unknown]
# gpg:                 aka "bcain" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6350 20F9 67A7 7164 79EF  49E0 175C 464E 541B 6D47
#      Subkey fingerprint: 3D66 AAE4 7459 4824 C88C  E0F8 1A54 AFB8 E564 6C32

* tag 'pull-hex-20231018' of https://github.com/quic/qemu:
  target/hexagon: fix some occurrences of -Wshadow=local
  target/hexagon: move GETPC() calls to top level helpers

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi 2023-10-30 13:42:29 +09:00
commit fd9a38fd43
6 changed files with 50 additions and 80 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
target/hexagon/imported/alu.idef
View File

@ -1142,9 +1142,9 @@ Q6INSN(A4_cround_rr,"Rd32=cround(Rs32,Rt32)",ATTRIBS(),"Convergent Round", {RdV
tmp128 = fSHIFTR128(tmp128, SHIFT);\
DST = fCAST16S_8S(tmp128);\
} else {\
size16s_t rndbit_128 = fCAST8S_16S((1LL << (SHIFT - 1))); \
size16s_t src_128 = fCAST8S_16S(SRC); \
size16s_t tmp128 = fADD128(src_128, rndbit_128);\
rndbit_128 = fCAST8S_16S((1LL << (SHIFT - 1))); \
src_128 = fCAST8S_16S(SRC); \
tmp128 = fADD128(src_128, rndbit_128);\
tmp128 = fSHIFTR128(tmp128, SHIFT);\
DST = fCAST16S_8S(tmp128);\
}

19
target/hexagon/macros.h
View File

@ -173,15 +173,6 @@
#define MEM_STORE8(VA, DATA, SLOT) \
MEM_STORE8_FUNC(DATA)(tcg_env, VA, DATA, SLOT)
#else
#define MEM_LOAD1s(VA) ((int8_t)mem_load1(env, pkt_has_store_s1, slot, VA))
#define MEM_LOAD1u(VA) ((uint8_t)mem_load1(env, pkt_has_store_s1, slot, VA))
#define MEM_LOAD2s(VA) ((int16_t)mem_load2(env, pkt_has_store_s1, slot, VA))
#define MEM_LOAD2u(VA) ((uint16_t)mem_load2(env, pkt_has_store_s1, slot, VA))
#define MEM_LOAD4s(VA) ((int32_t)mem_load4(env, pkt_has_store_s1, slot, VA))
#define MEM_LOAD4u(VA) ((uint32_t)mem_load4(env, pkt_has_store_s1, slot, VA))
#define MEM_LOAD8s(VA) ((int64_t)mem_load8(env, pkt_has_store_s1, slot, VA))
#define MEM_LOAD8u(VA) ((uint64_t)mem_load8(env, pkt_has_store_s1, slot, VA))
#define MEM_STORE1(VA, DATA, SLOT) log_store32(env, VA, DATA, 1, SLOT)
#define MEM_STORE2(VA, DATA, SLOT) log_store32(env, VA, DATA, 2, SLOT)
#define MEM_STORE4(VA, DATA, SLOT) log_store32(env, VA, DATA, 4, SLOT)
@ -530,8 +521,16 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val, int shift)
#ifdef QEMU_GENERATE
#define fLOAD(NUM, SIZE, SIGN, EA, DST) MEM_LOAD##SIZE##SIGN(DST, EA)
#else
#define MEM_LOAD1 cpu_ldub_data_ra
#define MEM_LOAD2 cpu_lduw_data_ra
#define MEM_LOAD4 cpu_ldl_data_ra
#define MEM_LOAD8 cpu_ldq_data_ra
#define fLOAD(NUM, SIZE, SIGN, EA, DST) \
DST = (size##SIZE##SIGN##_t)MEM_LOAD##SIZE##SIGN(EA)
do { \
check_noshuf(env, pkt_has_store_s1, slot, EA, SIZE, GETPC()); \
DST = (size##SIZE##SIGN##_t)MEM_LOAD##SIZE(env, EA, GETPC()); \
} while (0)
#endif
#define fMEMOP(NUM, SIZE, SIGN, EA, FNTYPE, VALUE)

2
target/hexagon/mmvec/macros.h
View File

@ -201,7 +201,7 @@
} while (0)
#define SCATTER_OP_WRITE_TO_MEM(TYPE) \
do { \
uintptr_t ra = GETPC(); \
ra = GETPC(); \
for (int i = 0; i < sizeof(MMVector); i += sizeof(TYPE)) { \
if (test_bit(i, env->vtcm_log.mask)) { \
TYPE dst = 0; \

84
target/hexagon/op_helper.c
View File

@ -95,9 +95,8 @@ void HELPER(debug_check_store_width)(CPUHexagonState *env, int slot, int check)
}
}
void HELPER(commit_store)(CPUHexagonState *env, int slot_num)
static void commit_store(CPUHexagonState *env, int slot_num, uintptr_t ra)
{
uintptr_t ra = GETPC();
uint8_t width = env->mem_log_stores[slot_num].width;
target_ulong va = env->mem_log_stores[slot_num].va;
@ -119,6 +118,12 @@ void HELPER(commit_store)(CPUHexagonState *env, int slot_num)
}
}
void HELPER(commit_store)(CPUHexagonState *env, int slot_num)
{
uintptr_t ra = GETPC();
commit_store(env, slot_num, ra);
}
void HELPER(gather_store)(CPUHexagonState *env, uint32_t addr, int slot)
{
mem_gather_store(env, addr, slot);
@ -127,10 +132,9 @@ void HELPER(gather_store)(CPUHexagonState *env, uint32_t addr, int slot)
void HELPER(commit_hvx_stores)(CPUHexagonState *env)
{
uintptr_t ra = GETPC();
int i;
/* Normal (possibly masked) vector store */
for (i = 0; i < VSTORES_MAX; i++) {
for (int i = 0; i < VSTORES_MAX; i++) {
if (env->vstore_pending[i]) {
env->vstore_pending[i] = 0;
target_ulong va = env->vstore[i].va;
@ -157,7 +161,7 @@ void HELPER(commit_hvx_stores)(CPUHexagonState *env)
g_assert_not_reached();
}
} else {
for (i = 0; i < sizeof(MMVector); i++) {
for (int i = 0; i < sizeof(MMVector); i++) {
if (test_bit(i, env->vtcm_log.mask)) {
cpu_stb_data_ra(env, env->vtcm_log.va[i],
env->vtcm_log.data.ub[i], ra);
@ -467,13 +471,12 @@ int32_t HELPER(cabacdecbin_pred)(int64_t RssV, int64_t RttV)
}
static void probe_store(CPUHexagonState *env, int slot, int mmu_idx,
bool is_predicated)
bool is_predicated, uintptr_t retaddr)
{
if (!is_predicated || !(env->slot_cancelled & (1 << slot))) {
size1u_t width = env->mem_log_stores[slot].width;
target_ulong va = env->mem_log_stores[slot].va;
uintptr_t ra = GETPC();
probe_write(env, va, width, mmu_idx, ra);
probe_write(env, va, width, mmu_idx, retaddr);
}
}
@ -494,16 +497,15 @@ void HELPER(probe_pkt_scalar_store_s0)(CPUHexagonState *env, int args)
int mmu_idx = FIELD_EX32(args, PROBE_PKT_SCALAR_STORE_S0, MMU_IDX);
bool is_predicated =
FIELD_EX32(args, PROBE_PKT_SCALAR_STORE_S0, IS_PREDICATED);
probe_store(env, 0, mmu_idx, is_predicated);
uintptr_t ra = GETPC();
probe_store(env, 0, mmu_idx, is_predicated, ra);
}
void HELPER(probe_hvx_stores)(CPUHexagonState *env, int mmu_idx)
static void probe_hvx_stores(CPUHexagonState *env, int mmu_idx,
uintptr_t retaddr)
{
uintptr_t retaddr = GETPC();
int i;
/* Normal (possibly masked) vector store */
for (i = 0; i < VSTORES_MAX; i++) {
for (int i = 0; i < VSTORES_MAX; i++) {
if (env->vstore_pending[i]) {
target_ulong va = env->vstore[i].va;
int size = env->vstore[i].size;
@ -538,6 +540,12 @@ void HELPER(probe_hvx_stores)(CPUHexagonState *env, int mmu_idx)
}
}
void HELPER(probe_hvx_stores)(CPUHexagonState *env, int mmu_idx)
{
uintptr_t retaddr = GETPC();
probe_hvx_stores(env, mmu_idx, retaddr);
}
void HELPER(probe_pkt_scalar_hvx_stores)(CPUHexagonState *env, int mask)
{
bool has_st0 = FIELD_EX32(mask, PROBE_PKT_SCALAR_HVX_STORES, HAS_ST0);
@ -547,18 +555,20 @@ void HELPER(probe_pkt_scalar_hvx_stores)(CPUHexagonState *env, int mask)
bool s0_is_pred = FIELD_EX32(mask, PROBE_PKT_SCALAR_HVX_STORES, S0_IS_PRED);
bool s1_is_pred = FIELD_EX32(mask, PROBE_PKT_SCALAR_HVX_STORES, S1_IS_PRED);
int mmu_idx = FIELD_EX32(mask, PROBE_PKT_SCALAR_HVX_STORES, MMU_IDX);
uintptr_t ra = GETPC();
if (has_st0) {
probe_store(env, 0, mmu_idx, s0_is_pred);
probe_store(env, 0, mmu_idx, s0_is_pred, ra);
}
if (has_st1) {
probe_store(env, 1, mmu_idx, s1_is_pred);
probe_store(env, 1, mmu_idx, s1_is_pred, ra);
}
if (has_hvx_stores) {
HELPER(probe_hvx_stores)(env, mmu_idx);
probe_hvx_stores(env, mmu_idx, ra);
}
}
#ifndef CONFIG_HEXAGON_IDEF_PARSER
/*
* mem_noshuf
* Section 5.5 of the Hexagon V67 Programmer's Reference Manual
@ -567,46 +577,16 @@ void HELPER(probe_pkt_scalar_hvx_stores)(CPUHexagonState *env, int mask)
* wasn't cancelled), we have to do the store first.
*/
static void check_noshuf(CPUHexagonState *env, bool pkt_has_store_s1,
uint32_t slot, target_ulong vaddr, int size)
uint32_t slot, target_ulong vaddr, int size,
uintptr_t ra)
{
if (slot == 0 && pkt_has_store_s1 &&
((env->slot_cancelled & (1 << 1)) == 0)) {
HELPER(probe_noshuf_load)(env, vaddr, size, MMU_USER_IDX);
HELPER(commit_store)(env, 1);
probe_read(env, vaddr, size, MMU_USER_IDX, ra);
commit_store(env, 1, ra);
}
}
uint8_t mem_load1(CPUHexagonState *env, bool pkt_has_store_s1,
uint32_t slot, target_ulong vaddr)
{
uintptr_t ra = GETPC();
check_noshuf(env, pkt_has_store_s1, slot, vaddr, 1);
return cpu_ldub_data_ra(env, vaddr, ra);
}
uint16_t mem_load2(CPUHexagonState *env, bool pkt_has_store_s1,
uint32_t slot, target_ulong vaddr)
{
uintptr_t ra = GETPC();
check_noshuf(env, pkt_has_store_s1, slot, vaddr, 2);
return cpu_lduw_data_ra(env, vaddr, ra);
}
uint32_t mem_load4(CPUHexagonState *env, bool pkt_has_store_s1,
uint32_t slot, target_ulong vaddr)
{
uintptr_t ra = GETPC();
check_noshuf(env, pkt_has_store_s1, slot, vaddr, 4);
return cpu_ldl_data_ra(env, vaddr, ra);
}
uint64_t mem_load8(CPUHexagonState *env, bool pkt_has_store_s1,
uint32_t slot, target_ulong vaddr)
{
uintptr_t ra = GETPC();
check_noshuf(env, pkt_has_store_s1, slot, vaddr, 8);
return cpu_ldq_data_ra(env, vaddr, ra);
}
#endif
/* Floating point */
float64 HELPER(conv_sf2df)(CPUHexagonState *env, float32 RsV)

9
target/hexagon/op_helper.h
View File

@ -19,15 +19,6 @@
#define HEXAGON_OP_HELPER_H
/* Misc functions */
uint8_t mem_load1(CPUHexagonState *env, bool pkt_has_store_s1,
uint32_t slot, target_ulong vaddr);
uint16_t mem_load2(CPUHexagonState *env, bool pkt_has_store_s1,
uint32_t slot, target_ulong vaddr);
uint32_t mem_load4(CPUHexagonState *env, bool pkt_has_store_s1,
uint32_t slot, target_ulong vaddr);
uint64_t mem_load8(CPUHexagonState *env, bool pkt_has_store_s1,
uint32_t slot, target_ulong vaddr);
void log_store64(CPUHexagonState *env, target_ulong addr,
int64_t val, int width, int slot);
void log_store32(CPUHexagonState *env, target_ulong addr,

10
target/hexagon/translate.c
View File

@ -553,7 +553,7 @@ static void gen_start_packet(DisasContext *ctx)
/* Preload the predicated registers into get_result_gpr(ctx, i) */
if (ctx->need_commit &&
!bitmap_empty(ctx->predicated_regs, TOTAL_PER_THREAD_REGS)) {
int i = find_first_bit(ctx->predicated_regs, TOTAL_PER_THREAD_REGS);
i = find_first_bit(ctx->predicated_regs, TOTAL_PER_THREAD_REGS);
while (i < TOTAL_PER_THREAD_REGS) {
tcg_gen_mov_tl(get_result_gpr(ctx, i), hex_gpr[i]);
i = find_next_bit(ctx->predicated_regs, TOTAL_PER_THREAD_REGS,
@ -566,7 +566,7 @@ static void gen_start_packet(DisasContext *ctx)
* Only endloop instructions conditionally write to pred registers
*/
if (ctx->need_commit && pkt->pkt_has_endloop) {
for (int i = 0; i < ctx->preg_log_idx; i++) {
for (i = 0; i < ctx->preg_log_idx; i++) {
int pred_num = ctx->preg_log[i];
ctx->new_pred_value[pred_num] = tcg_temp_new();
tcg_gen_mov_tl(ctx->new_pred_value[pred_num], hex_pred[pred_num]);
@ -575,7 +575,7 @@ static void gen_start_packet(DisasContext *ctx)
/* Preload the predicated HVX registers into future_VRegs and tmp_VRegs */
if (!bitmap_empty(ctx->predicated_future_vregs, NUM_VREGS)) {
int i = find_first_bit(ctx->predicated_future_vregs, NUM_VREGS);
i = find_first_bit(ctx->predicated_future_vregs, NUM_VREGS);
while (i < NUM_VREGS) {
const intptr_t VdV_off =
ctx_future_vreg_off(ctx, i, 1, true);
@ -588,7 +588,7 @@ static void gen_start_packet(DisasContext *ctx)
}
}
if (!bitmap_empty(ctx->predicated_tmp_vregs, NUM_VREGS)) {
int i = find_first_bit(ctx->predicated_tmp_vregs, NUM_VREGS);
i = find_first_bit(ctx->predicated_tmp_vregs, NUM_VREGS);
while (i < NUM_VREGS) {
const intptr_t VdV_off =
ctx_tmp_vreg_off(ctx, i, 1, true);
@ -1228,7 +1228,7 @@ void hexagon_translate_init(void)
offsetof(CPUHexagonState, mem_log_stores[i].data64),
store_val64_names[i]);
}
for (int i = 0; i < VSTORES_MAX; i++) {
for (i = 0; i < VSTORES_MAX; i++) {
snprintf(vstore_addr_names[i], NAME_LEN, "vstore_addr_%d", i);
hex_vstore_addr[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUHexagonState, vstore[i].va),