target/arm: Move pmsav8_mpu_lookup to ptw.c
This is the final user of get_phys_addr_pmsav7_default within helper.c, so make it static within ptw.c. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220604040607.269301-10-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
Peter Maydell
parent
730d5c31d8
commit
fedbaa0503
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@ -11834,142 +11834,6 @@ void v8m_security_lookup(CPUARMState *env, uint32_t address,
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}
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}
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bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
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MMUAccessType access_type, ARMMMUIdx mmu_idx,
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hwaddr *phys_ptr, MemTxAttrs *txattrs,
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int *prot, bool *is_subpage,
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ARMMMUFaultInfo *fi, uint32_t *mregion)
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{
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/* Perform a PMSAv8 MPU lookup (without also doing the SAU check
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* that a full phys-to-virt translation does).
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* mregion is (if not NULL) set to the region number which matched,
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* or -1 if no region number is returned (MPU off, address did not
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* hit a region, address hit in multiple regions).
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* We set is_subpage to true if the region hit doesn't cover the
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* entire TARGET_PAGE the address is within.
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*/
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ARMCPU *cpu = env_archcpu(env);
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bool is_user = regime_is_user(env, mmu_idx);
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uint32_t secure = regime_is_secure(env, mmu_idx);
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int n;
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int matchregion = -1;
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bool hit = false;
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uint32_t addr_page_base = address & TARGET_PAGE_MASK;
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uint32_t addr_page_limit = addr_page_base + (TARGET_PAGE_SIZE - 1);
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*is_subpage = false;
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*phys_ptr = address;
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*prot = 0;
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if (mregion) {
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*mregion = -1;
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}
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/* Unlike the ARM ARM pseudocode, we don't need to check whether this
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* was an exception vector read from the vector table (which is always
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* done using the default system address map), because those accesses
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* are done in arm_v7m_load_vector(), which always does a direct
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* read using address_space_ldl(), rather than going via this function.
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*/
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if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */
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hit = true;
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} else if (m_is_ppb_region(env, address)) {
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hit = true;
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} else {
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if (pmsav7_use_background_region(cpu, mmu_idx, is_user)) {
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hit = true;
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}
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for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) {
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/* region search */
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/* Note that the base address is bits [31:5] from the register
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* with bits [4:0] all zeroes, but the limit address is bits
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* [31:5] from the register with bits [4:0] all ones.
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*/
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uint32_t base = env->pmsav8.rbar[secure][n] & ~0x1f;
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uint32_t limit = env->pmsav8.rlar[secure][n] | 0x1f;
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if (!(env->pmsav8.rlar[secure][n] & 0x1)) {
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/* Region disabled */
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continue;
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}
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if (address < base || address > limit) {
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/*
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* Address not in this region. We must check whether the
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* region covers addresses in the same page as our address.
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* In that case we must not report a size that covers the
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* whole page for a subsequent hit against a different MPU
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* region or the background region, because it would result in
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* incorrect TLB hits for subsequent accesses to addresses that
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* are in this MPU region.
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*/
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if (limit >= base &&
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ranges_overlap(base, limit - base + 1,
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addr_page_base,
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TARGET_PAGE_SIZE)) {
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*is_subpage = true;
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}
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continue;
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}
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if (base > addr_page_base || limit < addr_page_limit) {
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*is_subpage = true;
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}
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if (matchregion != -1) {
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/* Multiple regions match -- always a failure (unlike
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* PMSAv7 where highest-numbered-region wins)
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*/
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fi->type = ARMFault_Permission;
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fi->level = 1;
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return true;
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}
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matchregion = n;
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hit = true;
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}
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}
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if (!hit) {
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/* background fault */
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fi->type = ARMFault_Background;
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return true;
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}
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if (matchregion == -1) {
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/* hit using the background region */
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get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
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} else {
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uint32_t ap = extract32(env->pmsav8.rbar[secure][matchregion], 1, 2);
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uint32_t xn = extract32(env->pmsav8.rbar[secure][matchregion], 0, 1);
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bool pxn = false;
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if (arm_feature(env, ARM_FEATURE_V8_1M)) {
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pxn = extract32(env->pmsav8.rlar[secure][matchregion], 4, 1);
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}
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if (m_is_system_region(env, address)) {
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/* System space is always execute never */
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xn = 1;
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}
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*prot = simple_ap_to_rw_prot(env, mmu_idx, ap);
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if (*prot && !xn && !(pxn && !is_user)) {
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*prot |= PAGE_EXEC;
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}
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/* We don't need to look the attribute up in the MAIR0/MAIR1
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* registers because that only tells us about cacheability.
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*/
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if (mregion) {
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*mregion = matchregion;
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}
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}
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fi->type = ARMFault_Permission;
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fi->level = 1;
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return !(*prot & (1 << access_type));
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}
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/* Combine either inner or outer cacheability attributes for normal
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* memory, according to table D4-42 and pseudocode procedure
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* CombineS1S2AttrHints() of ARM DDI 0487B.b (the ARMv8 ARM).
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146
target/arm/ptw.c
146
target/arm/ptw.c
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@ -375,9 +375,8 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
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return false;
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}
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void get_phys_addr_pmsav7_default(CPUARMState *env,
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ARMMMUIdx mmu_idx,
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int32_t address, int *prot)
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static void get_phys_addr_pmsav7_default(CPUARMState *env, ARMMMUIdx mmu_idx,
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int32_t address, int *prot)
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{
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if (!arm_feature(env, ARM_FEATURE_M)) {
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*prot = PAGE_READ | PAGE_WRITE;
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@ -605,6 +604,147 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
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return !(*prot & (1 << access_type));
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}
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bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
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MMUAccessType access_type, ARMMMUIdx mmu_idx,
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hwaddr *phys_ptr, MemTxAttrs *txattrs,
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int *prot, bool *is_subpage,
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ARMMMUFaultInfo *fi, uint32_t *mregion)
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{
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/*
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* Perform a PMSAv8 MPU lookup (without also doing the SAU check
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* that a full phys-to-virt translation does).
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* mregion is (if not NULL) set to the region number which matched,
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* or -1 if no region number is returned (MPU off, address did not
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* hit a region, address hit in multiple regions).
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* We set is_subpage to true if the region hit doesn't cover the
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* entire TARGET_PAGE the address is within.
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*/
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ARMCPU *cpu = env_archcpu(env);
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bool is_user = regime_is_user(env, mmu_idx);
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uint32_t secure = regime_is_secure(env, mmu_idx);
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int n;
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int matchregion = -1;
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bool hit = false;
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uint32_t addr_page_base = address & TARGET_PAGE_MASK;
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uint32_t addr_page_limit = addr_page_base + (TARGET_PAGE_SIZE - 1);
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*is_subpage = false;
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*phys_ptr = address;
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*prot = 0;
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if (mregion) {
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*mregion = -1;
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}
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/*
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* Unlike the ARM ARM pseudocode, we don't need to check whether this
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* was an exception vector read from the vector table (which is always
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* done using the default system address map), because those accesses
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* are done in arm_v7m_load_vector(), which always does a direct
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* read using address_space_ldl(), rather than going via this function.
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*/
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if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */
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hit = true;
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} else if (m_is_ppb_region(env, address)) {
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hit = true;
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} else {
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if (pmsav7_use_background_region(cpu, mmu_idx, is_user)) {
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hit = true;
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}
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for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) {
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/* region search */
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/*
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* Note that the base address is bits [31:5] from the register
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* with bits [4:0] all zeroes, but the limit address is bits
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* [31:5] from the register with bits [4:0] all ones.
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*/
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uint32_t base = env->pmsav8.rbar[secure][n] & ~0x1f;
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uint32_t limit = env->pmsav8.rlar[secure][n] | 0x1f;
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if (!(env->pmsav8.rlar[secure][n] & 0x1)) {
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/* Region disabled */
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continue;
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}
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if (address < base || address > limit) {
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/*
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* Address not in this region. We must check whether the
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* region covers addresses in the same page as our address.
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* In that case we must not report a size that covers the
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* whole page for a subsequent hit against a different MPU
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* region or the background region, because it would result in
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* incorrect TLB hits for subsequent accesses to addresses that
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* are in this MPU region.
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*/
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if (limit >= base &&
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ranges_overlap(base, limit - base + 1,
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addr_page_base,
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TARGET_PAGE_SIZE)) {
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*is_subpage = true;
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}
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continue;
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}
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if (base > addr_page_base || limit < addr_page_limit) {
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*is_subpage = true;
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}
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if (matchregion != -1) {
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/*
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* Multiple regions match -- always a failure (unlike
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* PMSAv7 where highest-numbered-region wins)
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*/
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fi->type = ARMFault_Permission;
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fi->level = 1;
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return true;
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}
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matchregion = n;
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hit = true;
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}
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}
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if (!hit) {
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/* background fault */
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fi->type = ARMFault_Background;
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return true;
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}
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if (matchregion == -1) {
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/* hit using the background region */
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get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
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} else {
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uint32_t ap = extract32(env->pmsav8.rbar[secure][matchregion], 1, 2);
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uint32_t xn = extract32(env->pmsav8.rbar[secure][matchregion], 0, 1);
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bool pxn = false;
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if (arm_feature(env, ARM_FEATURE_V8_1M)) {
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pxn = extract32(env->pmsav8.rlar[secure][matchregion], 4, 1);
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}
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if (m_is_system_region(env, address)) {
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/* System space is always execute never */
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xn = 1;
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}
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*prot = simple_ap_to_rw_prot(env, mmu_idx, ap);
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if (*prot && !xn && !(pxn && !is_user)) {
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*prot |= PAGE_EXEC;
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}
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/*
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* We don't need to look the attribute up in the MAIR0/MAIR1
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* registers because that only tells us about cacheability.
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*/
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if (mregion) {
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*mregion = matchregion;
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}
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}
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fi->type = ARMFault_Permission;
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fi->level = 1;
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return !(*prot & (1 << access_type));
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}
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static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
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MMUAccessType access_type, ARMMMUIdx mmu_idx,
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hwaddr *phys_ptr, MemTxAttrs *txattrs,
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@ -36,9 +36,6 @@ simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap)
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bool m_is_ppb_region(CPUARMState *env, uint32_t address);
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bool m_is_system_region(CPUARMState *env, uint32_t address);
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void get_phys_addr_pmsav7_default(CPUARMState *env,
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ARMMMUIdx mmu_idx,
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int32_t address, int *prot);
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bool pmsav7_use_background_region(ARMCPU *cpu, ARMMMUIdx mmu_idx, bool is_user);
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bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
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