Commit Graph

73451 Commits

Author SHA1 Message Date
Beata Michalska
0d57b49992 target/arm: Add support for DC CVAP & DC CVADP ins
ARMv8.2 introduced support for Data Cache Clean instructions
to PoP (point-of-persistence) - DC CVAP and PoDP (point-of-deep-persistence)
- DV CVADP. Both specify conceptual points in a memory system where all writes
that are to reach them are considered persistent.
The support provided considers both to be actually the same so there is no
distinction between the two. If none is available (there is no backing store
for given memory) both will result in Data Cache Clean up to the point of
coherency. Otherwise sync for the specified range shall be performed.

Signed-off-by: Beata Michalska <beata.michalska@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20191121000843.24844-5-beata.michalska@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16 10:46:35 +00:00
Beata Michalska
bd108a44bc migration: ram: Switch to ram block writeback
Switch to ram block writeback for pmem migration.

Signed-off-by: Beata Michalska <beata.michalska@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Acked-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Message-id: 20191121000843.24844-4-beata.michalska@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16 10:46:35 +00:00
Beata Michalska
61c490e25e Memory: Enable writeback for given memory region
Add an option to trigger memory writeback to sync given memory region
with the corresponding backing store, case one is available.
This extends the support for persistent memory, allowing syncing on-demand.

Signed-off-by: Beata Michalska <beata.michalska@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20191121000843.24844-3-beata.michalska@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16 10:46:35 +00:00
Beata Michalska
9e70492b43 tcg: cputlb: Add probe_read
Add probe_read alongside the write probing equivalent.

Signed-off-by: Beata Michalska <beata.michalska@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20191121000843.24844-2-beata.michalska@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16 10:46:35 +00:00
Niek Linnenbank
0c7f8c43da arm/arm-powerctl: set NSACR.{CP11, CP10} bits in arm_set_cpu_on()
This change ensures that the FPU can be accessed in Non-Secure mode
when the CPU core is reset using the arm_set_cpu_on() function call.
The NSACR.{CP11,CP10} bits define the exception level required to
access the FPU in Non-Secure mode. Without these bits set, the CPU
will give an undefined exception trap on the first FPU access for the
secondary cores under Linux.

This is necessary because in this power-control codepath QEMU
is effectively emulating a bit of EL3 firmware, and has to set
the CPU up as the EL3 firmware would.

Fixes: fc1120a7f5
Cc: qemu-stable@nongnu.org
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
[PMM: added clarifying para to commit message]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16 10:46:35 +00:00
Marc Zyngier
f96f3d5f09 target/arm: Add support for missing Jazelle system registers
QEMU lacks the minimum Jazelle implementation that is required
by the architecture (everything is RAZ or RAZ/WI). Add it
together with the HCR_EL2.TID0 trapping that goes with it.

Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20191201122018.25808-6-maz@kernel.org
[PMM: moved ARMCPRegInfo array to file scope, marked it
 'static global', moved new condition down in
 register_cp_regs_for_features() to go with other feature
 things rather than up with the v6/v7/v8 stuff]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16 10:46:35 +00:00
Marc Zyngier
5bb0a20b74 target/arm: Handle AArch32 CP15 trapping via HSTR_EL2
HSTR_EL2 offers a way to trap ranges of CP15 system register
accesses to EL2, and it looks like this register is completely
ignored by QEMU.

To avoid adding extra .accessfn filters all over the place (which
would have a direct performance impact), let's add a new TB flag
that gets set whenever HSTR_EL2 is non-zero and that QEMU translates
a context where this trap has a chance to apply, and only generate
the extra access check if the hypervisor is actively using this feature.

Tested with a hand-crafted KVM guest accessing CBAR.

Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20191201122018.25808-5-maz@kernel.org
[PMM: use is_a64(); fix comment syntax]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16 10:46:35 +00:00
Marc Zyngier
9ca1d776cb target/arm: Handle trapping to EL2 of AArch32 VMRS instructions
HCR_EL2.TID3 requires that AArch32 reads of MVFR[012] are trapped to
EL2, and HCR_EL2.TID0 does the same for reads of FPSID.
In order to handle this, introduce a new TCG helper function that
checks for these control bits before executing the VMRC instruction.

Tested with a hacked-up version of KVM/arm64 that sets the control
bits for 32bit guests.

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20191201122018.25808-4-maz@kernel.org
[PMM: move helper declaration to helper.h; make it
 TCG_CALL_NO_WG]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16 10:46:34 +00:00
Marc Zyngier
93fbc983b2 target/arm: Honor HCR_EL2.TID1 trapping requirements
HCR_EL2.TID1 mandates that access from EL1 to REVIDR_EL1, AIDR_EL1
(and their 32bit equivalents) as well as TCMTR, TLBTR are trapped
to EL2. QEMU ignores it, making it harder for a hypervisor to
virtualize the HW (though to be fair, no known hypervisor actually
cares).

Do the right thing by trapping to EL2 if HCR_EL2.TID1 is set.

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20191201122018.25808-3-maz@kernel.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16 10:46:34 +00:00
Marc Zyngier
630fcd4d2b target/arm: Honor HCR_EL2.TID2 trapping requirements
HCR_EL2.TID2 mandates that access from EL1 to CTR_EL0, CCSIDR_EL1,
CCSIDR2_EL1, CLIDR_EL1, CSSELR_EL1 are trapped to EL2, and QEMU
completely ignores it, making it impossible for hypervisors to
virtualize the cache hierarchy.

Do the right thing by trapping to EL2 if HCR_EL2.TID2 is set.

Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20191201122018.25808-2-maz@kernel.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16 10:46:34 +00:00
Cédric Le Goater
ccb88bf220 aspeed: Change the "nic" property definition
The Aspeed MII model has a link pointing to its associated FTGMAC100
NIC in the machine.

Change the "nic" property definition so that it explicitly sets the
pointer. The property isn't optional : not being able to set the link
is a bug and QEMU should rather abort than exit in this case.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20191119141211.25716-18-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16 10:46:34 +00:00
Cédric Le Goater
2ec11f2320 aspeed: Change the "scu" property definition
The Aspeed Watchdog and Timer models have a link pointing to the SCU
controller model of the machine.

Change the "scu" property definition so that it explicitly sets the
pointer. The property isn't optional : not being able to set the link
is a bug and QEMU should rather abort than exit in this case.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20191119141211.25716-17-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16 10:46:34 +00:00
PanNengyuan
15cea92d9e gpio: fix memory leak in aspeed_gpio_init()
Address Sanitizer shows memory leak in hw/gpio/aspeed_gpio.c:875

Reported-by: Euler Robot <euler.robot@huawei.com>
Signed-off-by: PanNengyuan <pannengyuan@huawei.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20191119141211.25716-16-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16 10:46:34 +00:00
Cédric Le Goater
63ceb818a4 aspeed: Add support for the tacoma-bmc board
The Tacoma BMC board is replacement board for the BMC of the OpenPOWER
Witherspoon system. It uses a AST2600 SoC instead of a AST2500 and the
I2C layout is the same as it controls the same main board. Used for HW
bringup.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20191119141211.25716-15-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16 10:46:34 +00:00
Cédric Le Goater
baa4732bc1 aspeed: Remove AspeedBoardConfig array and use AspeedMachineClass
AspeedBoardConfig is a redundant way to define class attributes and it
complexifies the machine definition and initialization.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20191119141211.25716-14-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16 10:46:34 +00:00
Cédric Le Goater
f286f04c21 aspeed/smc: Add AST2600 timings registers
Each CS has its own Read Timing Compensation Register on newer SoCs.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20191119141211.25716-13-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16 10:46:34 +00:00
Cédric Le Goater
2175eacfcd aspeed/smc: Do not map disabled segment on the AST2600
The segments can be disabled on the AST2600 (zero register value).
CS0 is open by default but not the other CS. This is closing the
access to the flash device in user mode and forbids scanning.

In the model, check the segment size and disable the associated region
when the value is zero.

Fixes: bcaa8ddd08 ("aspeed/smc: Add AST2600 support")
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20191119141211.25716-12-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16 10:46:34 +00:00
Cédric Le Goater
673b1f8650 aspeed/smc: Restore default AHB window mapping at reset
The current model only restores the Segment Register values but leaves
the previous CS mapping behind. Introduce a helper setting the
register value and mapping the region at the requested address. Use
this helper when a Segment register is set and at reset.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20191119141211.25716-11-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16 10:46:34 +00:00
Joel Stanley
28c80f15fc watchdog/aspeed: Fix AST2600 frequency behaviour
The AST2600 control register sneakily changed the meaning of bit 4
without anyone noticing. It no longer controls the 1MHz vs APB clock
select, and instead always runs at 1MHz.

The AST2500 was always 1MHz too, but it retained bit 4, making it read
only. We can model both using the same fixed 1MHz calculation.

Fixes: 6b2b2a703c ("hw: wdt_aspeed: Add AST2600 support")
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20191119141211.25716-10-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16 10:46:34 +00:00
Joel Stanley
aabf1de4b7 watchdog/aspeed: Improve watchdog timeout message
Users benefit from knowing which watchdog timer has expired. The address
of the watchdog's registers unambiguously indicates which has expired,
so log that.

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20191119141211.25716-9-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16 10:46:34 +00:00
Joel Stanley
310b5bc692 aspeed/scu: Fix W1C behavior
This models the clock write one to clear registers, and fixes up some
incorrect behavior in all of the write to clear registers.

There was also a typo in one of the register definitions.

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20191119141211.25716-8-clg@kaod.org
[clg: checkpatch.pl fixes ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16 10:46:34 +00:00
Joel Stanley
d3ff9e69b7 aspeed/sdmc: Make ast2600 default 1G
Most boards have this much.

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20191119141211.25716-7-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16 10:46:34 +00:00
Cédric Le Goater
66cc84a1a3 aspeed/i2c: Add trace events
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Tested-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20191119141211.25716-6-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16 10:46:34 +00:00
Cédric Le Goater
545d6bef70 aspeed/i2c: Add support for DMA transfers
The I2C controller of the Aspeed AST2500 and AST2600 SoCs supports DMA
transfers to and from DRAM.

A pair of registers defines the buffer address and the length of the
DMA transfer. The address should be aligned on 4 bytes and the maximum
length should not exceed 4K. The receive or transmit DMA transfer can
then be initiated with specific bits in the Command/Status register of
the controller.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Tested-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20191119141211.25716-5-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16 10:46:34 +00:00
Cédric Le Goater
95b56e173e aspeed: Add a DRAM memory region at the SoC level
Currently, we link the DRAM memory region to the FMC model (for DMAs)
through a property alias at the SoC level. The I2C model will need a
similar region for DMA support, add a DRAM region property at the SoC
level for both model to use.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Tested-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20191119141211.25716-4-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16 10:46:34 +00:00
Cédric Le Goater
aab90b1cac aspeed/i2c: Check SRAM enablement on AST2500
The SRAM must be enabled before using the Buffer Pool mode or the DMA
mode. This is not required on other SoCs.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Tested-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20191119141211.25716-3-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16 10:46:34 +00:00
Cédric Le Goater
6054fc73e8 aspeed/i2c: Add support for pool buffer transfers
The Aspeed I2C controller can operate in different transfer modes :

  - Byte Buffer mode, using a dedicated register to transfer a
    byte. This is what the model supports today.

  - Pool Buffer mode, using an internal SRAM to transfer multiple
    bytes in the same command sequence.

Each SoC has different SRAM characteristics. On the AST2400, 2048
bytes of SRAM are available at offset 0x800 of the controller AHB
window. The pool buffer can be configured from 1 to 256 bytes per bus.

On the AST2500, the SRAM is at offset 0x200 and the pool buffer is of
16 bytes per bus.

On the AST2600, the SRAM is at offset 0xC00 and the pool buffer is of
32 bytes per bus. It can be splitted in two for TX and RX but the
current model does not add support for it as it it unused by known
drivers.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Tested-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20191119141211.25716-2-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16 10:46:34 +00:00
David Gibson
1625073289 exynos4210_gic: Suppress gcc9 format-truncation warnings
exynos4210_gic_realize() prints the number of cpus into some temporary
buffers, but it only allows 3 bytes space for it.  That's plenty:
existing machines will only ever set this value to EXYNOS4210_NCPUS
(2).  But the compiler can't always figure that out, so some[*] gcc9
versions emit -Wformat-truncation warnings.

We can fix that by hinting the constraint to the compiler with a
suitably placed assert().

[*] The bizarre thing here, is that I've long gotten these warnings
    compiling in a 32-bit x86 container as host - Fedora 30 with
    gcc-9.2.1-1.fc30.i686 - but it compiles just fine on my normal
    x86_64 host - Fedora 30 with and gcc-9.2.1-1.fc30.x86_64.

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
[PMM: deleted stray blank line]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16 10:46:34 +00:00
Christophe Lyon
cf7beda507 target/arm: Add support for cortex-m7 CPU
This is derived from cortex-m4 description, adding DP support and FPv5
instructions with the corresponding flags in isar and mvfr2.

Checked that it could successfully execute
vrinta.f32 s15, s15
while cortex-m4 emulation rejects it with "illegal instruction".

Signed-off-by: Christophe Lyon <christophe.lyon@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20191025090841.10299-1-christophe.lyon@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16 10:46:34 +00:00
Peter Maydell
084a398bf8 Pull request
-----BEGIN PGP SIGNATURE-----
 
 iQEzBAABCAAdFiEEhpWov9P5fNqsNXdanKSrs4Grc8gFAl3zoOsACgkQnKSrs4Gr
 c8jeYQgAvpGixIk4yPRhxlbWmOyNao0ves8F8HE0JAbGxKHo12/EJQFAoe7H+fBe
 pNNAzOCGZUF5YplXcrHdwmrDCjCQTWUT6deAKMbUoUJrw6nOxyCQJDuV5Xzuxvbn
 ekou59uLRFGnVnBKNlVnYXJuN0AKoEAnM2Z6qnrjhBvecYVooZAJO8XTAwbQoese
 2fs5fqcEz9SOYsGPd55DahCAt8DKxBqJ4lugq6KdztxS3/2KWgXASKJtsWXsmVFX
 YeUo2Y1zo35JbvwDtGtXOTo8DTzxiHPqHDA9Jm4mL0W7nPHUvpHS+5bmFhwyF/qz
 /2M1/zOt3YXnwR2V15c3/IaekoOk2g==
 =UNxY
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into staging

Pull request

# gpg: Signature made Fri 13 Dec 2019 14:32:11 GMT
# gpg:                using RSA key 8695A8BFD3F97CDAAC35775A9CA4ABB381AB73C8
# gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" [full]
# gpg:                 aka "Stefan Hajnoczi <stefanha@gmail.com>" [full]
# Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35  775A 9CA4 ABB3 81AB 73C8

* remotes/stefanha/tags/block-pull-request:
  iothread: document -object iothread on man page
  virtio-blk: advertise F_WCE (F_FLUSH) if F_CONFIG_WCE is advertised

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-13 18:14:07 +00:00
Peter Maydell
4148d142a8 virtiofs pull 2019-12-13: Minor fixes and cleanups
Cleanup from Marc-André and MSI-X fix from Stefan.
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCAAdFiEERfXHG0oMt/uXep+pBRYzHrxb/ecFAl3ze80ACgkQBRYzHrxb
 /eesrw//aYIhGN7m6rHfQ8gMdwknMxdPGDOgOiby83mFKxKVsKXgWR8wXX03vk2S
 I4vCWPWXL8FadmyZ3UlpXRR24EzrxRhcAHG+SxOPt/v5SaDP/o4+SZd9fP1KfthF
 a+kgfCZK767KcUqYov2D4cqqI3EkIj6i9LwqyvenGV6EPaNIe+5rswhflVIPGfEF
 wAN+3wRiG9B1StLHEQyNfmUnYHG0E10BMdK48kPle+a/YaL98RJgRtVzEyhtxCQD
 vc0SK8DX0LAijXxJC/kGCdgqaAhQnRjZnoR4zXyKQy5PuxtwaMd3ncQzNicy0VhG
 1vnmHljM00aK6qaW8GvE8dQAznlkjk8w9tT+OcTidY3mYBnQKXNYkn5dLrwjllQX
 mb5H2FT9pR3QKVxscxf4k3wg0ZXVZLyxYI+25IgecJ36qpNY2JLikrYzsdVr5AwE
 RkQWacTfF7XBn2Zw4zlW4OVamAHDqd0Dnx7DySXPdlEJIaG9wi1FVMGGOOlk0rdB
 ZrAEGpWhsV7FD4hwAHuchpoYILV80I6hhoU84ZU1ayo21RrHYOJOFF476zx7bHVm
 MnQRJjsM3wHxGtbZ7clDks+zlxuSS23hlrKJxGNNy9xNcryBoZu4cz8eS99hmohO
 pIEncZyTfA+tFqvAtKQ9Q/ygyOkDyYJ9oKVV7iUE/y6cvvBQoGk=
 =eO9a
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/dgilbert/tags/pull-virtiofs-20191213a' into staging

virtiofs pull 2019-12-13: Minor fixes and cleanups

Cleanup from Marc-André and MSI-X fix from Stefan.

# gpg: Signature made Fri 13 Dec 2019 11:53:49 GMT
# gpg:                using RSA key 45F5C71B4A0CB7FB977A9FA90516331EBC5BFDE7
# gpg: Good signature from "Dr. David Alan Gilbert (RH2) <dgilbert@redhat.com>" [full]
# Primary key fingerprint: 45F5 C71B 4A0C B7FB 977A  9FA9 0516 331E BC5B FDE7

* remotes/dgilbert/tags/pull-virtiofs-20191213a:
  virtio-fs: fix MSI-X nvectors calculation
  vhost-user-fs: remove "vhostfd" property

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-13 15:58:54 +00:00
Peter Maydell
35081f79fa - conversion of virtfs-proxy-helper from libcap to libcap-ng
- removal of libcap-dev from docker, travis and gitlab CI
 - removal of deprecate "-virtfs_synth" option
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCAAdFiEEtIKLr5QxQM7yo0kQcdTV5YIvc9YFAl3ym0kACgkQcdTV5YIv
 c9YzNhAAoVGEBUgEGqDhmqU42g34Texs5Of3NPk7IPl471T7pnK4bKSNLzk77ib6
 VuknfywHBnljTNBr+3am6A6N8icAkeADkr/gXFt/WPeLdByPuVH6K9Ome4jFuFT3
 7mxuH4fKSfLGO4VuuHy1ezGs3upOsQZysKdMFVp6JaoyfGYga/CKGxbBdy1M2iR9
 vcRFK9zVbqixuMXDH+K9iGXtJG+voJdFitMhvuraNZK1tGrXiiXRl01FaUxnYgzS
 mnm+qgWOP05u7gIfpAN9BYPIz2FvyKu+xJNPwXYXzJMyd4mHg6DDxFnpV3e9a7Nq
 rxSvdt4mO9jacFuuWS4MROAkVlatSc12bjseiIMqLp8fqg7GJ1AIa/5CqBN3Rmmb
 yxS8ck7EKV5AQDH//aG+uXy2XhgqBh+iK07udJJfoTDKJMwTNfTqDbJmtnUREZFf
 paIfi92H+qBWxML6eFcqMw1mzKXS5Lqad/8o+Ma2Cmh4GVABlFOZiSoNli8EwHUp
 BnBTBNehiSLYQe3XP00clboo4x4ySRVeZA8MlGDO0OFqNzHV7pW29Oh+mbDsH/S+
 3CL3j/9sqO0tAFaMlZULh0L7d5Vn1Pc2LV+XYMuZy6sYoMeCrHslcaZUevQ6aap5
 z5y1vXCQtXWw3wsFcKgKIsgIh5HIH6bQIc/fdI4578Y4yoIi19M=
 =ms/Q
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/gkurz/tags/9p-next-2019-12-12' into staging

- conversion of virtfs-proxy-helper from libcap to libcap-ng
- removal of libcap-dev from docker, travis and gitlab CI
- removal of deprecate "-virtfs_synth" option

# gpg: Signature made Thu 12 Dec 2019 19:55:53 GMT
# gpg:                using RSA key B4828BAF943140CEF2A3491071D4D5E5822F73D6
# gpg: Good signature from "Greg Kurz <groug@kaod.org>" [full]
# gpg:                 aka "Gregory Kurz <gregory.kurz@free.fr>" [full]
# gpg:                 aka "[jpeg image of size 3330]" [full]
# Primary key fingerprint: B482 8BAF 9431 40CE F2A3  4910 71D4 D5E5 822F 73D6

* remotes/gkurz/tags/9p-next-2019-12-12:
  virtfs: Remove the deprecated "-virtfs_synth" option
  travis.yml: Drop libcap-dev
  ci: Use libcap-ng
  docker: remove libcap development packages
  virtfs-proxy-helper: switch from libcap to libcap-ng

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-13 13:47:45 +00:00
Peter Maydell
ba9975025e Open 5.0 development tree
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-13 11:59:06 +00:00
Stefan Hajnoczi
86d2a49b41 iothread: document -object iothread on man page
Add -object iothread documentation to the man page, including references
to the query-iothread QMP command and qom-set syntax for adjusting
adaptive polling parameters at run-time.

Reported-by: Zhenyu Ye <yezhenyu2@huawei.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-id: 20191025122236.29815-1-stefanha@redhat.com
Message-Id: <20191025122236.29815-1-stefanha@redhat.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2019-12-13 11:24:07 +00:00
Evgeny Yakovlev
5f2585772f virtio-blk: advertise F_WCE (F_FLUSH) if F_CONFIG_WCE is advertised
Virtio spec 1.1 (and earlier), 5.2.5.2 Driver Requirements: Device
Initialization:

"Devices SHOULD always offer VIRTIO_BLK_F_FLUSH, and MUST offer it if
they offer VIRTIO_BLK_F_CONFIG_WCE"

Currently F_CONFIG_WCE and F_WCE are not connected to each other.
Qemu will advertise F_CONFIG_WCE if config-wce argument is
set for virtio-blk device. And F_WCE is advertised only if
underlying block backend actually has it's caching enabled.

Fix this by advertising F_WCE if F_CONFIG_WCE is also advertised.

To preserve backwards compatibility with newer machine types make this
behaviour governed by "x-enable-wce-if-config-wce" virtio-blk-device
property and introduce hw_compat_4_2 with new property being off by
default for all machine types <= 4.2 (but don't introduce 4.3
machine type itself yet).

Signed-off-by: Evgeny Yakovlev <wrfsh@yandex-team.ru>
Message-Id: <1572978137-189218-1-git-send-email-wrfsh@yandex-team.ru>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2019-12-13 11:22:06 +00:00
Stefan Hajnoczi
366844f3d1 virtio-fs: fix MSI-X nvectors calculation
The following MSI-X vectors are required:
 * VIRTIO Configuration Change
 * hiprio virtqueue
 * requests virtqueues

Fix the calculation to reserve enough MSI-X vectors.  Otherwise guest
drivers fall back to a sub-optional configuration where all virtqueues
share a single vector.

This change does not break live migration compatibility since
vhost-user-fs-pci devices are not migratable yet.

Reported-by: Vivek Goyal <vgoyal@redhat.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-Id: <20191209110759.35227-1-stefanha@redhat.com>
Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2019-12-13 10:53:57 +00:00
Marc-André Lureau
7038573487 vhost-user-fs: remove "vhostfd" property
The property doesn't make much sense for a vhost-user device.

Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20191116112016.14872-1-marcandre.lureau@redhat.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2019-12-13 10:38:58 +00:00
Peter Maydell
b0ca999a43 Update version for v4.2.0 release
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-12 16:45:57 +00:00
Peter Maydell
52901abf94 Update version for v4.2.0-rc5 release
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-10 17:15:21 +00:00
Thomas Huth
b3e2bb9458 virtfs: Remove the deprecated "-virtfs_synth" option
It's been marked as deprecated since QEMU v4.1, time to remove it now.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Greg Kurz <groug@kaod.org>
2019-12-09 18:00:35 +01:00
Greg Kurz
26f603d4f8 travis.yml: Drop libcap-dev
Commit 7e46261368 converted virtfs-proxy-helper to using libcap-ng. There
aren't any users of libcap anymore. No need to install libcap-dev.

Signed-off-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Acked-by: Alex Bennée <alex.bennee@linaro.org>
2019-12-09 18:00:22 +01:00
Dr. David Alan Gilbert
24e15a0b69 ci: Use libcap-ng
We currently enable libcap-dev in build-clang to pick up the 9p proxy
helper.  Paolo's patch changes (commit 7e46261368) that to use
libcap-ng, so switch to using it.  This also means we'll be testing the
scsi pr manager and the bridge helper.

Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Acked-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
[groug, mention SHA1 that dropped libcap]
Signed-off-by: Greg Kurz <groug@kaod.org>
2019-12-09 18:00:08 +01:00
Paolo Bonzini
ad430dd9da docker: remove libcap development packages
Libcap was dropped from virtio-9p (commit 7e46261368), so remove it from
the dockerfiles as well.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Acked-by: Alex Bennée <alex.bennee@linaro.org>
[groug, mention SHA1 that dropped libcap]
Signed-off-by: Greg Kurz <groug@kaod.org>
2019-12-09 17:59:33 +01:00
Peter Maydell
9b4efa2ede bitmap fix for 4.2-rc5
- Fix a regression that broke bitmap deletion without a transaction,
 and causes a crash with transaction (only transaction is new to 4.2),
 when a qcow2 file contains persistent bitmaps from prior shutdown
 -----BEGIN PGP SIGNATURE-----
 
 iQEzBAABCAAdFiEEccLMIrHEYCkn0vOqp6FrSiUnQ2oFAl3uaBMACgkQp6FrSiUn
 Q2rX+Af8Dn6cklzAizMLWCvXgEmbUhEvcVp5Gc9w34McCYokQaFDtNDuoShDIksa
 F01uP3TlKYd8JoMiGihqVP1mcof8dyGBNMX1fVr2iYIet0h7OAtzOfatXiHmaz4g
 r3utlx+0BHm+m9jhwsnCKp24ERa9izGmFQAIyaFLarGdasr29ArepCEXGXiOwtYF
 RwD+ioolN9wDcOHjRrEVLHKKRkiX9dSnxKxENahf+M2hVXD+UfbX4cumYxBWOxJQ
 qJpTznTA3BxRzUd3/Ue6NL0YmKmXLqHzyeX2Nc1NsdC485nCKn/QZtgI/8yAU0uL
 6nseBGa1kgF4+97LwGmPKUmumcxGmQ==
 =YAZ1
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2019-12-09' into staging

bitmap fix for 4.2-rc5

- Fix a regression that broke bitmap deletion without a transaction,
and causes a crash with transaction (only transaction is new to 4.2),
when a qcow2 file contains persistent bitmaps from prior shutdown

# gpg: Signature made Mon 09 Dec 2019 15:28:19 GMT
# gpg:                using RSA key 71C2CC22B1C4602927D2F3AAA7A16B4A2527436A
# gpg: Good signature from "Eric Blake <eblake@redhat.com>" [full]
# gpg:                 aka "Eric Blake (Free Software Programmer) <ebb9@byu.net>" [full]
# gpg:                 aka "[jpeg image of size 6874]" [full]
# Primary key fingerprint: 71C2 CC22 B1C4 6029 27D2  F3AA A7A1 6B4A 2527 436A

* remotes/ericb/tags/pull-nbd-2019-12-09:
  block/qcow2-bitmap: fix crash bug in qcow2_co_remove_persistent_dirty_bitmap

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-09 16:06:51 +00:00
Vladimir Sementsov-Ogievskiy
f56281abd9 block/qcow2-bitmap: fix crash bug in qcow2_co_remove_persistent_dirty_bitmap
Here is double bug:

First, return error but not set errp. This may lead to:
qmp block-dirty-bitmap-remove may report success when actually failed

block-dirty-bitmap-remove used in a transaction will crash, as
qmp_transaction will think that it returned success and will call
block_dirty_bitmap_remove_commit which will crash, as state->bitmap is
NULL

Second (like in anecdote), this case is not an error at all. As it is
documented in the comment above bdrv_co_remove_persistent_dirty_bitmap
definition, absence of bitmap is not an error, and similar case handled
at start of qcow2_co_remove_persistent_dirty_bitmap, it returns 0 when
there is no bitmaps at all.

But when there are some bitmaps, but not the requested one, it return
error with errp unset.

Fix that.

Trigger:
1. create persistent bitmap A
2. shutdown vm  (bitmap A is synced)
3. start vm
4. create persistent bitmap B
5. remove bitmap B - it fails (and crashes if in transaction)

Potential workaround (rather invasive to ask clients to implement it):
1. create persistent bitmap A
2. shutdown vm
3. start vm
4. create persistent bitmap B
5. remember, that we want to remove bitmap B after vm shutdown
...
  some other operations
...
6. vm shutdown
7. start vm in stopped mode, and remove all bitmaps marked for removing
8. stop vm

Fixes: b56a1e3175
Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Message-Id: <20191205193049.30666-1-vsementsov@virtuozzo.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: John Snow <jsnow@redhat.com>
[eblake: commit message tweaks]
Signed-off-by: Eric Blake <eblake@redhat.com>
2019-12-09 09:23:04 -06:00
Peter Maydell
8350b17be0 ppc patch queue 2019-12-09
This is a last minute pull request for ppc-for-4.2.  I know it's very
 late in freeze, but this does fix a regression: a bad interaction
 between the new qemu and SLOF device tree construction code means that
 SLOF will crash if PCI to PCI bridges are included in the system.
 
 This PR supersedes ppc-for-4.2-20191206.  This one has only a more
 minimal change to the firmware addressed only at fixing this bug and
 not incorporating some other unrelated changes that happened in the
 meantime.
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCAAdFiEEdfRlhq5hpmzETofcbDjKyiDZs5IFAl3t0wMACgkQbDjKyiDZ
 s5Jfsg//c8aRcQLJDYmdrMdmSh9t2rhXBG7lM+kRYa914HM9J3+Zk03NRJYmeEYn
 NP05Vek0r6EE603dtHujcepfX5PiU5702fENv6aqSun24uionIVsN6NH8CElY93/
 KcDY5xeNX9XOkZ2m6q+QRK8SxgSmB0fEgpQg2pcC3L5zCd7LQ4psaT/lCDY4Mvix
 9l7WdrWKfY5GLZ1F54jX9Rulu4p8Bcy9jTkrddfyQK0/NMjuT3TsnJKt/CSGU0ar
 CjTxxf8C2UTObXB2N6DPRruKQ2sB8Dwx6YXHY9k7pShRiFtBXAJBLOdawX/5MXXq
 DYKl6hw0RNrzcGbyH4fgcIC7X/GoaAf+GSW3c0C6umHo+A63LTjnPvaPhM/Tzdw6
 Z4UnWFZ+xVOuKBc1PAjTEzoQtnoxa8Rn9glnTKtgQ7N/GTwoTMmwLCA7zrbGOyk9
 o1rx/87QpAob6idzZIxNWhNqQIFhKtAz9BjsCfpJIQDDPn2o+NbAQIU/QPKgN0LQ
 rIpXDBM94jjhDkQ4S9HoqwI74AGQjzvUcT59bSsYpYD2UYZAjwAYEIj6gbOgpvJB
 Hu1ujhl50gwgVGxYcfrxoJvURIsroaDNSYVyYVlnZBqIz83SE6LTyzas1GmDsgz5
 GIGPMSr6aYKMTgRnDbHHs48bE1UGPybgnAek/tS5Ei3qoV5JJMs=
 =ZWDP
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-4.2-20191209' into staging

ppc patch queue 2019-12-09

This is a last minute pull request for ppc-for-4.2.  I know it's very
late in freeze, but this does fix a regression: a bad interaction
between the new qemu and SLOF device tree construction code means that
SLOF will crash if PCI to PCI bridges are included in the system.

This PR supersedes ppc-for-4.2-20191206.  This one has only a more
minimal change to the firmware addressed only at fixing this bug and
not incorporating some other unrelated changes that happened in the
meantime.

# gpg: Signature made Mon 09 Dec 2019 04:52:19 GMT
# gpg:                using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392
# gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full]
# gpg:                 aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full]
# gpg:                 aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" [full]
# gpg:                 aka "David Gibson (kernel.org) <dwg@kernel.org>" [unknown]
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E  87DC 6C38 CACA 20D9 B392

* remotes/dgibson/tags/ppc-for-4.2-20191209:
  pseries: Update SLOF firmware image

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-09 11:07:34 +00:00
Alexey Kardashevskiy
a2fad86497 pseries: Update SLOF firmware image
This fixes PCI bridge regression.

Alexey Kardashevskiy (3):
      ibm,client-architecture-support: Fix stack handling
      fdt: Fix updating the tree at H_CAS
      version: update to 20191209

Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-12-09 12:16:26 +11:00
Peter Maydell
02f9c885ed * fix for x86 KVM on older kernels (Yang Zhong)
-----BEGIN PGP SIGNATURE-----
 
 iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAl3qPSgUHHBib256aW5p
 QHJlZGhhdC5jb20ACgkQv/vSX3jHroMaPAf/d9qRoE2EBrvz2gYksEz4WY0BpyyG
 1QX5U3cF3DNXWyqbB2gWMR/O7h4cxYBr8u9tTFVUjhAK69fNqm0lACfhkmhUjeMx
 Nh1Hy3JW9wDadUk/8jEmxGH+vJcJW5wV6PJtyKYTGGkpA4ZvUIY7xSea4MlfrqPr
 mpBk3GR2ItsQh+IEyItfQrNWSqKEiHjxejsb8DsM0qkJSudT462vyL2BjVEvIF3Z
 uQPO5U8flSeR1mgAqIGOP98Db1iWPBOCAwDW62W18CH5t64Q7ZTTB+nPP+MrLoPm
 IMkRr1zKMJFX+z20Sl/E3NoQ1cLVr0bMFN792uNKR0qFEXyhsQM/CFRHRQ==
 =T82y
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging

* fix for x86 KVM on older kernels (Yang Zhong)

# gpg: Signature made Fri 06 Dec 2019 11:36:08 GMT
# gpg:                using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
# gpg:                issuer "pbonzini@redhat.com"
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full]
# gpg:                 aka "Paolo Bonzini <pbonzini@redhat.com>" [full]
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4  E2F7 7E15 100C CD36 69B1
#      Subkey fingerprint: F133 3857 4B66 2389 866C  7682 BFFB D25F 78C7 AE83

* remotes/bonzini/tags/for-upstream:
  target/i386: disable VMX features if nested=0

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-06 15:05:20 +00:00
Yang Zhong
2605188240 target/i386: disable VMX features if nested=0
If kvm does not support VMX feature by nested=0, the kvm_vmx_basic
can't get the right value from MSR_IA32_VMX_BASIC register, which
make qemu coredump when qemu do KVM_SET_MSRS.

The coredump info:
error: failed to set MSR 0x480 to 0x0
kvm_put_msrs: Assertion `ret == cpu->kvm_msr_buf->nmsrs' failed.

Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20191206071111.12128-1-yang.zhong@intel.com>
Reported-by: Catherine Ho <catherine.hecx@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-12-06 12:35:40 +01:00
Peter Maydell
1bdc319ab5 Update version for v4.2.0-rc4 release
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-03 17:56:30 +00:00