Commit Graph

13 Commits

Author SHA1 Message Date
Peter Maydell 200bf596b9 target-arm: Fix 11MPCore cache type register value
Make the 11MPCore report a valid value in its cache type register
(the previous value appears to have been incorrectly copied from
the 1136/1176). In particular, do not report that we have an
aliasing VIPT cache, because this causes Linux to attempt to use
the v6 block cache ops which the 11MPCore doesn't actually have.
(This causes no problems currently because we over-broadly provide
those ops on all cores, but prevents us correctly narrowing the
block ops down to those cores which actually implement them.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20 12:00:58 +00:00
Peter Maydell c5fad12fa0 target-arm: Move A9 config_base_address reset value to ARMCPU
Move the A9 config_base_address cp15 register reset value to
ARMCPU. This should become a QOM property so that the Highbank
board can set it without having to pull in cpu-qom.h, but at
least this avoids the implicit dependency on reset ordering
that the previous workaround had.

Cc: Mark Langsdorf <mark.langsdorf@calxeda.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-04-27 11:06:18 +00:00
Andreas Färber 778c3a0619 target-arm: Change cpu_arm_init() return type to ARMCPU
Make cpu_arm_init() return a QOM ARMCPU, so that we don't need to
obtain an ARMCPU through arm_env_get_cpu() in machine init code.
This requires to adjust the inclusion site of cpu-qom.h and in turn,
forward-looking, to homogenize its include order.

cpu_init() must still return a CPUARMState for backwards and
cross-target compatibility, so adjust the cpu_init macro.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-27 11:04:44 +00:00
Peter Maydell 3c30dd5a68 target-arm: Move reset handling to arm_cpu_reset
Now that cpu_reset_model_id() has gone we can move the
reset code over to the class reset function and have cpu_state_reset
simply do a reset on the CPU QOM object.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Andreas Färber <afaerber@suse.de>
2012-04-21 18:13:22 +00:00
Peter Maydell 85df3786b2 target-arm: Move cache ID register setup to cpu specific init fns
Move cache ID register reset out of cpu_reset_model_id() by
creating a field for the reset value in ARMCPU and setting it
up in the cpu specific init functions.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Andreas Färber <afaerber@suse.de>
2012-04-21 18:12:29 +00:00
Peter Maydell 2e4d7e3e3e target-arm: Move feature register setup to per-CPU init fns
Move feature register value setup to per-CPU init functions.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Andreas Färber <afaerber@suse.de>
2012-04-21 18:11:38 +00:00
Peter Maydell 0ca7e01cbc target-arm: Move SCTLR reset value setup to per cpu init fns
Move the reset value of SCTLR to ARMCPU, initialised in
the per-cpu init functions. It can then be reset by a
simple copy, and we can drop the code from cpu_reset_model_id().

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Andreas Färber <afaerber@suse.de>
2012-04-21 18:10:44 +00:00
Peter Maydell 64e1671fd4 target-arm: Move CTR setup to per cpu init fns
Move CTR (cache type register) value to an ARMCPU field
set up by per-cpu init fns.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Andreas Färber <afaerber@suse.de>
2012-04-21 18:09:53 +00:00
Peter Maydell bd35c3553b target-arm: Move MVFR* setup to per cpu init fns
Move the MVFR* VFP feature register values to ARMCPU,
so they are set up by the implementation-specific instance
init functions rather than in cpu_reset_model_id().

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Andreas Färber <afaerber@suse.de>
2012-04-21 18:09:00 +00:00
Peter Maydell 325b3ceff6 target-arm: Move FPSID config to cpu init fns
Move the reset FPSID to the ARMCPU struct, and set it in the
per-implementation instance init function. At reset we then
just copy the reset value into the CPUARMState field.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Andreas Färber <afaerber@suse.de>
2012-04-21 18:08:12 +00:00
Peter Maydell 581be09434 target-arm: Move feature bit settings to CPU init fns
Move the setting of the feature bits from cpu_reset_model_id()
to each CPU's instance init function. This requires us to move
the features field in CPUARMState so that it is not cleared
on reset.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Andreas Färber <afaerber@suse.de>
2012-04-21 18:07:21 +00:00
Peter Maydell 777dc78411 target-arm: Add QOM subclasses for each ARM cpu implementation
Register subclasses for each ARM CPU implementation.

Let arm_cpu_list() enumerate CPU subclasses in alphabetical order,
except for special value "any".

Replace cpu_arm_find_by_name()'s string -> CPUID lookup by storing the
CPUID (aka MIDR, Main ID Register) value in the class.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-21 18:06:27 +00:00
Andreas Färber dec9c2d430 target-arm: Minimalistic CPU QOM'ification
Introduce only one non-abstract type TYPE_ARM_CPU and do not touch
cp15 registers to not interfere with Peter's ongoing remodelling.
Embed CPUARMState as first (additional) field of ARMCPU.

Let CPUClass::reset() call cpu_state_reset() for now.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-03-29 15:42:50 +00:00