Commit Graph

29 Commits

Author SHA1 Message Date
Max Filippov d0ce7e9cfc target/xtensa: fix timers test
The value of CCOUNT special register is calculated as time elapsed
since CCOUNT == 0 multiplied by the core frequency. In icount mode time
increment between consecutive instructions that don't involve time
warps is constant, but unless the result of multiplication of this
constant by the core frequency is a whole number the CCOUNT increment
between these instructions may not be constant. E.g. with icount=7 each
instruction takes 128ns, with core clock of 10MHz CCOUNT values for
consecutive instructions are:

  502: (128 * 502 * 10000000) / 1000000000 = 642.56
  503: (128 * 503 * 10000000) / 1000000000 = 643.84
  504: (128 * 504 * 10000000) / 1000000000 = 645.12

I.e.the CCOUNT increments depend on the absolute time. This results in
varying CCOUNT differences for consecutive instructions in tests that
involve time warps and don't set CCOUNT explicitly.

Change frequency of the core used in tests so that clock cycle takes
exactly 64ns. Change icount power used in tests to 6, so that each
instruction takes exactly 1 clock cycle. With these changes CCOUNT
increments only depend on the number of executed instructions and that's
what timer tests expect, so they work correctly.

Longer story:
  http://lists.nongnu.org/archive/html/qemu-devel/2018-03/msg04326.html

Cc: Pavel Dovgaluk <Pavel.Dovgaluk@ispras.ru>
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-03-26 14:17:04 -07:00
Max Filippov e55239e2b6 target/xtensa: tests: fix memctl SR test
memctl SR is not available on dc232b, as it was introduced in more
recent hardware release. Now that this information is available through
the libisa the test fails. Fix the test.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-01-09 09:55:38 -08:00
Max Filippov 8b912ff033 target/xtensa: tests: clean up interrupt tests
Don't use hardcoded software interrupt masks, use XCHAL macros.
Mask off timer interrupt bits that are not checked for.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-01-15 13:36:09 -08:00
Max Filippov 255d254382 target/xtensa: tests: add memctl test
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-01-15 13:01:56 -08:00
Max Filippov 0a362d0768 target/xtensa: tests: add ccount write tests
Check that CCOUNT SR is writable and that CCOMPARE timers are updated
when CCOUNT is written to.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-01-15 13:01:56 -08:00
Max Filippov 4f89b41c28 target/xtensa: tests: replace hardcoded interrupt masks
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-01-15 13:01:56 -08:00
Max Filippov 72b3b8f24a target/xtensa: tests: fix timer tests
Don't expect that CCOUNT increments are equal to the number of executed
instructions. Verify that timer interrupt does not fire before the
programmed CCOMPARE value and does fire after.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-01-15 13:01:56 -08:00
Max Filippov 122d302053 target/xtensa: tests: run tests with icount
Timer tests expect certain determinism in CCOUNT updates and timer
interrupts firing. Run QEMU with -icount to get deterministic results.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-01-15 13:01:56 -08:00
Thomas Huth fcf5ef2ab5 Move target-* CPU file into a target/ folder
We've currently got 18 architectures in QEMU, and thus 18 target-xxx
folders in the root folder of the QEMU source tree. More architectures
(e.g. RISC-V, AVR) are likely to be included soon, too, so the main
folder of the QEMU sources slowly gets quite overcrowded with the
target-xxx folders.
To disburden the main folder a little bit, let's move the target-xxx
folders into a dedicated target/ folder, so that target-xxx/ simply
becomes target/xxx/ instead.

Acked-by: Laurent Vivier <laurent@vivier.eu> [m68k part]
Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> [tricore part]
Acked-by: Michael Walle <michael@walle.cc> [lm32 part]
Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> [s390x part]
Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> [s390x part]
Acked-by: Eduardo Habkost <ehabkost@redhat.com> [i386 part]
Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> [sparc part]
Acked-by: Richard Henderson <rth@twiddle.net> [alpha part]
Acked-by: Max Filippov <jcmvbkbc@gmail.com> [xtensa part]
Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [ppc part]
Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> [cris&microblaze part]
Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn> [unicore32 part]
Signed-off-by: Thomas Huth <thuth@redhat.com>
2016-12-20 21:52:12 +01:00
Markus Armbruster a9c94277f0 Use #include "..." for our own headers, <...> for others
Tracked down with an ugly, brittle and probably buggy Perl script.

Also move includes converted to <...> up so they get included before
ours where that's obviously okay.

Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Tested-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2016-07-12 16:19:16 +02:00
Max Filippov 85d36377e4 target-xtensa: test cross-page opcode
Alter cross-page TB test to also test cross-page opcode.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-12-17 05:49:32 +03:00
Max Filippov 09c7fbef76 target-xtensa: add entry overflow test
Check that entry instruction raises window overflow exception when
PS.CALLINC points to live registers.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-11-10 17:59:13 +03:00
Max Filippov 20303e42d4 target-xtensa: tests: pre-process tests linker script
Xtensa cores have configurable interrupt vectors and endiannes. This
information is needed to link executable images correctly for a specific
core configuration. Instead of hard-coding dc232 defaults pull endianness,
number of high-priority interrupts and location of vectors from the core
configuration and pass it through the C preprocessor.

While at it clean up tabs and align the initial stack on 16 bytes.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-11-03 00:51:43 +03:00
Max Filippov 57a740514d target-xtensa: add tests for cross-page TB
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-05-26 12:33:54 +04:00
Max Filippov ca3164df4d target-xtensa: completely clean TLB between MMU tests
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-05-26 12:33:54 +04:00
Max Filippov 2c09eee112 target-xtensa: add basic tests for cache opcodes
Test that non-locking prefetch operations don't cause exceptions on
missing TLB and that other 'hit' cache operations do.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-02-24 04:47:02 +04:00
Max Filippov a2e67072b7 target-xtensa: allow using core configuration in tests
Add path to the core configuration directory to test build command and
replace .include asm directive with #include to enable preprocessing.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-02-24 04:47:01 +04:00
Max Filippov d0fa1f0df3 target-xtensa: add overridable test_init macro
Some test suites, like MMU, need per-test initialization. Don't make them
redefine test macro, add test_init for that purpose.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-02-24 04:47:01 +04:00
Andreas Färber aaa2ebc567 tests/tcg/xtensa: Fix out-of-tree build
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2013-07-29 18:35:45 +04:00
Max Filippov 7be9d0e6d1 target-xtensa: add extui unit test
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2013-07-29 18:24:26 +04:00
Max Filippov 5dacd229eb target-xtensa: add s32c1i unit tests
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-12-08 18:48:26 +00:00
Max Filippov efdfac94f4 target-xtensa: add SR accessibility unit tests
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-12-08 18:48:26 +00:00
Max Filippov c305e32f43 target-xtensa: add MMU pagewalking tests
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-06-09 10:45:03 +00:00
Max Filippov 536a98d4d6 target-xtensa: add tests for LOOPNEZ and LOOPGTZ
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-04-21 13:24:50 +00:00
Max Filippov ad4ccc9370 target-xtensa: add test for IBREAK invalidation
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-04-14 15:25:39 +00:00
Max Filippov ec9fe93efe target-xtensa: add tests for LBEG/LEND invalidation
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-04-14 15:25:39 +00:00
Max Filippov 7d6b9f0a38 target-xtensa: improve unit tests debugging
- add testcase announcement;
- add global symbols for individual tests;
- add host-debug-* makefile target.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2012-04-14 03:48:08 +04:00
Max Filippov e7dfa64def target-xtensa: add breakpoint tests
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2012-02-20 20:07:12 +04:00
Anthony Liguori c09015dd04 tests: mv tests/* -> tests/tcg
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-01-12 10:03:28 -06:00