OpenE2K/qemu-e2k
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220 Commits

Author SHA1 Message Date
Paolo Bonzini
f08b617018 softmmu: introduce cpu_ldst.h 
This will collect all load and store helpers soon.  For now
it is just a replacement for softmmu_exec.h, which this patch
stops including directly, but we also include it where this will
be necessary in order to simplify the next patch.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
 2014-06-05 16:10:33 +02:00
Richard Henderson
2ef6175aa7 tcg: Invert the inclusion of helper.h 
Rather than include helper.h with N values of GEN_HELPER, include a
secondary file that sets up the macros to include helper.h.  This
minimizes the files that must be rebuilt when changing the macros
for file N.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2014-05-28 09:33:54 -07:00
Richard Henderson
214bb280c6 target-alpha: Fix RDUSP 
Commit 06ef8604e9 contained a typo.

Signed-off-by: Richard Henderson <rth@twiddle.net>
 2014-05-02 20:42:02 -07:00
Richard Henderson
06ef8604e9 target-alpha: Remove cpu_unique, cpu_sysval, cpu_usp 
Technically, these variables could have been referenced both via
offsets from env and as TCG registers, which would be illegal.
Of course, that could only be done from PALcode, and ours doesn't
do that.

But honestly, these are used infrequently enough that they don't
really need to be TCG registers.  We wind up with exactly the same
code if we follow the letter of the law and issue explicit ld/st.

Signed-off-by: Richard Henderson <rth@twiddle.net>
 2014-04-17 11:47:42 -07:00
Richard Henderson
39acc64741 target-alpha: Tidy alpha_translate_init 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2014-04-17 11:47:42 -07:00
Richard Henderson
e566be049a target-alpha: Don't issue goto_tb under singlestep 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2014-04-17 11:47:42 -07:00
Richard Henderson
8f811b9a4a target-alpha: Use non-local temps for zero/sink 
These values are no longer live across branches.

Signed-off-by: Richard Henderson <rth@twiddle.net>
 2014-04-17 11:47:42 -07:00
Richard Henderson
a9e05a1ceb target-alpha: Use extract to get insn fields 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2014-04-17 11:47:42 -07:00
Richard Henderson
0e154fe92c target-alpha: Convert mfpr/mtpr to source/sink 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2014-04-17 11:47:42 -07:00
Richard Henderson
ef3765cb95 target-alpha: Convert gen_cpys et al to source/sink 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2014-04-17 11:47:42 -07:00
Richard Henderson
e8d8fef48f target-alpha: Convert gen_fcvtlq/ql to source/sink 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2014-04-17 11:47:42 -07:00
Richard Henderson
6580935246 target-alpha: Convert gen_fcmov to source/sink 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2014-04-17 11:47:42 -07:00
Richard Henderson
76bff4f82f target-alpha: Convert gen_bcond to source/sink 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2014-04-17 11:47:42 -07:00
Richard Henderson
e20b8c04a3 target-alpha: Convert most ieee insns to source/sink 
This one fixes a bug, previously noted as supressing exceptions
in the (unlikely) case the destination register was $f31.

Signed-off-by: Richard Henderson <rth@twiddle.net>
 2014-04-17 11:47:42 -07:00
Richard Henderson
8b0190bbde target-alpha: Convert gen_ieee_input to source/sink 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2014-04-17 11:47:42 -07:00
Richard Henderson
f477ed3c11 target-alpha: Convert MVIOP2 to source/sink 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2014-04-17 11:47:42 -07:00
Richard Henderson
cd2754addc target-alpha: Convert ARITH3 to source/sink 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2014-04-17 11:47:42 -07:00
Richard Henderson
3d045dbca5 target-alpha: Convert FARITH3 to source/sink 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2014-04-17 11:47:42 -07:00
Richard Henderson
baee04abba target-alpha: Convert FARITH2 to source/sink 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2014-04-17 11:47:42 -07:00
Richard Henderson
b144be9e06 target-alpha: Convert gen_zap/not to source/sink 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2014-04-17 11:47:42 -07:00
Richard Henderson
5e5863ecf1 target-alpha: Convert gen_ins_h/l to source/sink 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2014-04-17 11:47:42 -07:00
Richard Henderson
9a734d64f9 target-alpha: Convert gen_ext_h/l to source/sink 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2014-04-17 11:47:42 -07:00
Richard Henderson
9a8fa1bdad target-alpha: Convert gen_msk_h/l to source/sink 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2014-04-17 11:47:41 -07:00
Richard Henderson
83ebb7cd01 target-alpha: Convert gen_cmov to source/sink 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2014-04-17 11:47:41 -07:00
Richard Henderson
42774a56ec target-alpha: Convert ARITH3_EX to source/sink 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2014-04-17 11:47:41 -07:00
Richard Henderson
958683482c target-alpha: Convert gen_cmp to source/sink 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2014-04-17 11:47:41 -07:00
Richard Henderson
cd2d46fd21 target-alpha: Convert gen_store_conditional to source/sink 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2014-04-17 11:47:41 -07:00
Richard Henderson
595b8fdd54 target-alpha: Convert gen_load/store_mem to source/sink 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2014-04-17 11:47:41 -07:00
Richard Henderson
a4af30447b target-alpha: Convert opcode 0x1F to source/sink 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2014-04-17 11:47:41 -07:00
Richard Henderson
46010969f3 target-alpha: Convert opcode 0x1E to source/sink 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2014-04-17 11:47:41 -07:00
Richard Henderson
c67b67e511 target-alpha: Convert opcode 0x1C to source/sink 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2014-04-17 11:47:41 -07:00
Richard Henderson
1eaa1da7e4 target-alpha: Convert opcode 0x1B to source/sink 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2014-04-17 11:47:41 -07:00
Richard Henderson
8f56ced8aa target-alpha: Convert opcode 0x1A to source/sink 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2014-04-17 11:47:41 -07:00
Richard Henderson
89fe090bb3 target-alpha: Convert opcode 0x18 to source/sink 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2014-04-17 11:47:41 -07:00
Richard Henderson
6b88b37c0e target-alpha: Convert opcode 0x17 to source/sink 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2014-04-17 11:47:41 -07:00
Richard Henderson
075b8ddb9b target-alpha: Convert opcode 0x14 to source/sink 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2014-04-17 11:47:41 -07:00
Richard Henderson
de4d3555fa target-alpha: Convert opcode 0x13 to source/sink 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2014-04-17 11:47:41 -07:00
Richard Henderson
3bd67b7dab target-alpha: Convert opcode 0x12 to source/sink 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2014-04-17 11:47:41 -07:00
Richard Henderson
db4a16458c target-alpha: Convert opcode 0x11 to source/sink 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2014-04-17 11:47:41 -07:00
Richard Henderson
194cfb43d5 target-alpha: Introduce functions for source/sink 
This will allow cleaner handling of $31 and $f31.
Convert opcodes 0x08, 0x09, 0x10 as examples.

Signed-off-by: Richard Henderson <rth@twiddle.net>
 2014-04-17 11:47:40 -07:00
Richard Henderson
64f45e4991 target-alpha: Introduce REQUIRE_REG_31 
We were missing quite a few checks for Ra or Rb required to be 31.
Further, the one place we did check we also checked for no literal
operand and the Handbook says nothing about that.

Signed-off-by: Richard Henderson <rth@twiddle.net>
 2014-04-17 11:47:40 -07:00
Richard Henderson
5238c88657 target-alpha: Introduce REQUIRE_TB_FLAG 
The methods by which we check for cpu features varied wildly
across the function.  Using a nice macro cleans this up.

Signed-off-by: Richard Henderson <rth@twiddle.net>
 2014-04-17 11:47:40 -07:00
Paolo Bonzini
67debe3ae5 target-alpha: fix the braces 
Conform to coding style, and avoid further occurrences of bugs due to
misplaced braces.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2014-04-17 11:47:40 -07:00
Paolo Bonzini
83d1c8ae88 target-alpha: fix subl and s8subl indentation 
Two missing braces, one close and one open, fabulously let the code
compile.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
 2014-03-17 13:21:12 +01:00
Andreas Färber
f0c3c505a8 cpu: Move breakpoints field from CPU_COMMON to CPUState 
Most targets were using offsetof(CPUFooState, breakpoints) to determine
how much of CPUFooState to clear on reset. Use the next field after
CPU_COMMON instead, if any, or sizeof(CPUFooState) otherwise.

Signed-off-by: Andreas Färber <afaerber@suse.de>
 2014-03-13 19:20:47 +01:00
Edgar E. Iglesias
ab1da85791 exec: Make stl_*_phys input an AddressSpace 
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
 2014-02-11 22:57:18 +10:00
Edgar E. Iglesias
f606604f1c exec: Make stq_*_phys input an AddressSpace 
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
 2014-02-11 22:57:12 +10:00
Edgar E. Iglesias
2c17449b30 exec: Make ldq/ldub_*_phys input an AddressSpace 
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
 2014-02-11 22:57:00 +10:00
Edgar E. Iglesias
fdfba1a298 exec: Make ldl_*_phys input an AddressSpace 
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
 2014-02-11 22:56:54 +10:00
Stefan Weil
73f395fa88 misc: New spelling fixes in comments 
compatiblity -> compatibility
continously -> continuously
existance -> existence
usefull -> useful
shoudl -> should

Signed-off-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
 2013-10-26 13:01:57 +04:00