Commit Graph

269 Commits

Author SHA1 Message Date
Aurelien Jarno 6a957025eb tcg: improve output log
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-07 07:53:41 +02:00
Aurelien Jarno 94f4af02a1 tcg: allocate s->op_dead_iargs dynamically
Similarly to what is already done in tcg_liveness_analysis() when
USE_LIVENESS_ANALYSIS is not set.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-04 15:30:44 +02:00
Aurelien Jarno 8389c67b82 tcg: remove dead code
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-04 15:16:46 +02:00
Aurelien Jarno 5f0ce17ffc tcg/i386: add support for ext{8,16}u_i32 TCG ops
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-04 13:24:45 +02:00
Aurelien Jarno 6458421802 tcg/x86_64: add support for ext{8,16,32}u_i{32,64} TCG ops
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-04 13:24:45 +02:00
Aurelien Jarno cfc86988a8 tcg: add ext{8,16,32}u_i{32,64} TCG ops
Currently zero extensions ops are implemented by a and op with a
constant. This is then catched in some backend, and replaced by
a zero extension instruction. While this works well on RISC
machines, this adds a useless register move on non-RISC machines.

Example on x86:
  ext16u_i32 r1, r2
is translated into
  mov    %eax,%ebx
  movzwl %bx, %ebx
while the optimized version should be:
  movzwl %ax, %ebx

This patch adds ext{8,16,32}u_i{32,64} TCG ops that can be
implemented in the backends to avoid emitting useless register
moves.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-04 13:24:45 +02:00
Aurelien Jarno d68592022b Revert part of 6692b04319
Committed by accident.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-30 14:16:12 +02:00
Aurelien Jarno 6692b04319 TCG: fix DEF2 macro
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-30 14:10:34 +02:00
Aurelien Jarno 17cf428f2e tcg/i386: generates dec/inc instead of sub/add when possible
We must take care that dec/inc do not compute CF, which is needed by
add2/sub2.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-27 20:00:39 +02:00
Aurelien Jarno b70650cbfe tcg/i386: optimize and $0xff(ff), reg
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-27 20:00:38 +02:00
Aurelien Jarno a4b18c6ddb tcg/x86_64: generated dec/inc instead of sub/add when possible
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-27 18:08:16 +02:00
malc d937032764 tcg/ppc: always use tcg_out_call
Signed-off-by: malc <av1474@comtv.ru>
2009-09-27 14:41:14 +04:00
Laurent Desnogues 7990496dcb ARM back-end: Use sxt[bh] instructions for ext{8, 6}s
This patch uses sxtb for ext8s_i32 and sxth for ext16s_i32 in ARM back-end.

Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-26 21:29:59 +02:00
Stefan Weil d89c682f20 Suppress some variants of English in comments
Replace surpress, supress by suppress.

Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-25 16:31:35 +02:00
Blue Swirl 96e132e24e Compile TCG runtime library only once
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-09-20 19:06:34 +00:00
Stefan Weil b348113d21 tcg: fix size of local variables in tcg_gen_bswap64_i64
t0, t1 must be 64 bit values, not 32 bit.

Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-16 21:26:47 +02:00
malc abb6ae2c00 X86_64: Use proper jumps/calls when displacement exceeds +-2G
Signed-off-by: malc <av1474@comtv.ru>
2009-09-11 01:38:52 +04:00
malc c45851c44a When targeting PPU use rlwinm instead of andi. if possible
andi. is microcoded and slow there.

Signed-off-by: malc <av1474@comtv.ru>
2009-09-06 07:24:37 +04:00
Laurent Desnogues 4e6f6d4c20 ARM back-end: Fix encode_imm
the encode_imm function in tcg/arm/tcg-target.c lacks shift declaration.

Laurent

Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2009-08-25 01:14:14 +02:00
Laurent Desnogues 94953e6d74 ARM back-end: Handle all possible immediates for ALU ops
this patch handles all possible constants for immediate operand of ALU ops.
I'm not very satisfied by the implementation.

Laurent

Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2009-08-22 14:29:09 +02:00
Laurent Desnogues f878d2d235 ARM back-end: Add TCG not
this patch:

 - implements TCG not.

Laurent

Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2009-08-22 13:55:06 +02:00
Juan Quintela e2542fe2bc rename WORDS_BIGENDIAN to HOST_WORDS_BIGENDIAN
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-07-27 14:09:21 -05:00
Juan Quintela 092c73eeff rename DEBUG_TCG to CONFIG_DEBUG_TCG
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-07-27 14:09:21 -05:00
Juan Quintela dfe5fff3ea change HOST_SOLARIS to CONFIG_SOLARIS{_VERSION}
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-07-27 14:09:16 -05:00
Blue Swirl 871e6c3507 Fix CONFIG_PROFILER
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-07-21 12:18:03 +00:00
malc a71836de38 Fix rbase initialization
Signed-off-by: malc <av1474@comtv.ru>
2009-07-20 01:15:23 +04:00
Laurent Desnogues cb4e581fae this patch improves the ARM back-end in the following way:
- use movw/movt to load immediate values for ARMv7-A
- implement add/sub/and/or/xor with immediate (only 8-bit)

Laurent

Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2009-07-18 14:20:30 +02:00
Aurelien Jarno d9885a0b9e tcg: Fix tcg_gen_rotr_i64
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-07-18 11:32:56 +02:00
malc f6548c0a4b PPC 32/64 GUEST_BASE support
Signed-off-by: malc <av1474@comtv.ru>
2009-07-18 13:16:36 +04:00
malc 4f4a67ae78 Fix LHZX opcode value
Signed-off-by: malc <av1474@comtv.ru>
2009-07-18 13:16:13 +04:00
Juan Quintela adea8197b4 Userspace guest address offsetting
Fix type in i386 tcg.

Signed-off-by: Juan Quintela <quintela@redhat.com>
2009-07-17 19:50:18 +01:00
Paul Brook 379f6698d7 Userspace guest address offsetting
Re-implement GUEST_BASE support.
Offset guest ddress space by default if the guest binary contains
regions below the host mmap_min_addr.
Implement support for i386, x86-64 and arm hosts.

Signed-off-by: Riku Voipio <riku.voipio@iki.fi>
Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-07-17 13:12:41 +01:00
Paul Brook 2d69f3590d ARM host fixes
Minor TCG cleanups and warning fixes for ARM hosts.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-07-17 11:21:12 +01:00
Paul Brook 5561650587 Include assert.h from qemu-common.h
Include assert.h from qemu-common.h and remove other direct uses.
cpu-all.h still need to include it because of the dyngen-exec.h hacks

Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-05-13 20:54:26 +01:00
aurel32 cca8298291 tcg: make sure NDEBUG is defined before including <assert.h>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7122 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-16 09:58:30 +00:00
aurel32 f839394688 Add a --enable-debug-tcg option to configure
This patch allows DEBUG_TCGV to be defined (and also prevents NDEBUG
from being defined) when passing an option to the configure script.
This should help to prevent any accidental changes that enable
DEBUG_TCGV in tcg/tcg.h from being committed in future, and may
help to encourage testing with DEBUG_TCGV enabled.

Signed-off-by: Stuart Brady <stuart.brady@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7105 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-13 18:45:38 +00:00
malc 2ffebe2dcb Remove reserved registers from tcg_target_reg_alloc_order
Noticed by Andreas Faerber

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7082 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-11 08:19:50 +00:00
malc 9de187a099 Whack [LS]MW
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7081 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-11 07:39:04 +00:00
malc e23f2f36b1 Remove reserved registers from tcg_target_reg_alloc_order
Noticed by Andreas Faerber

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7080 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-11 07:38:56 +00:00
aurel32 3e00b3f538 tcg/tcg.h: fix a few typos
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7024 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-07 19:57:24 +00:00
aurel32 b9c18f5658 tcg: add a CONST flag to TCG helpers
A const function only reads its arguments and does not use TCG
globals variables. Hence a call to such a function does not
save TCG globals variabes back to their canonical location.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7008 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-06 12:33:59 +00:00
aurel32 34d5a9ff63 tcg: improve comment about pure functions
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7007 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-06 12:33:51 +00:00
aurel32 79d342dc6b tcg/x86_64: optimize register allocation order
The beginning of the register allocation order list on the TCG x86_64
target matches the list of clobbered registers. This means that when an
helper is called, there is almost always clobbered registers that have
to be spilled.

The same way register %rsi and %rdi are at the top of the register
allocation order list, while they can't be used for load/store
operations. This means the data and/or address registers are very often
%rsi and %rdi, and their values have to be spilled, and then moved back
to another register.

This patches changes to the allocation order to avoid those effects.
It results in a 8% gain speed in qemu-x86_64 to compress a bzip2 file,
and a 6% gain in qemu-system-mips64 to compile a small application.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7003 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-05 20:08:50 +00:00
blueswir1 1da92db280 Fix branches and TLB matches for 64 bit targets
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6974 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-04 19:10:26 +00:00
blueswir1 f843e5282a Allocate space for static call args, increase stack frame size on Sparc64
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6973 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-04 15:33:03 +00:00
aurel32 864951afdd tcg: fix _tl aliases for divu/remu
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6948 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-29 14:08:54 +00:00
aurel32 ab36421e54 tcg: add _tl aliases for div/divu/rem/remu
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6939 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-29 01:19:22 +00:00
aurel32 604457d702 tcg/README: fix description of bswap32_i32/i64
Thanks to Stuart Brady for the notice.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6920 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-28 23:27:30 +00:00
aurel32 86dbdd4012 tcg/x86_64: add bswap16_i{32,64} and bswap32_i64 ops
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6838 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-13 09:35:55 +00:00
aurel32 5d40cd6302 tcg/x86: add bswap16_i32 ops
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6837 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-13 09:35:49 +00:00