Commit Graph

136 Commits

Author SHA1 Message Date
Bastian Koppelmann fcecf12684 target-tricore: Add SRC_MOV_E instruction of the v1.6 ISA
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2015-05-22 17:02:33 +02:00
Bastian Koppelmann 6d2afc8a5e target-tricore: introduce ISA v1.6.1 feature
The aurix platform contains of several different cpu models and uses
the 1.6.1 ISA. This patch changes the generic aurix model to the more
specific tc27x cpu model and sets specific features.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2015-05-22 17:02:33 +02:00
Bastian Koppelmann fd5ecf31d4 target-tricore: Add ISA v1.3.1 cpu and fix tc1796 to using v1.3
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2015-05-22 17:02:33 +02:00
Bastian Koppelmann 3446a11181 target-tricore: fix rfe not restoring the PC
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2015-05-11 14:25:49 +02:00
Bastian Koppelmann bc72f8aaf2 target-tricore: fix rslcx restoring the upper context instead of the lower
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2015-05-11 14:25:41 +02:00
Bastian Koppelmann 4959d6b366 target-tricore: fix BO_OFF10_SEXT calculating the wrong offset
The lower part of the combined offset was sign extended and could lead to
wrong results.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2015-05-11 14:15:46 +02:00
Bastian Koppelmann 7bd0eaec31 target-tricore: fix SLR_LD_W and SLR_LD_W_POSTINC insn being a 2 byte memory access insted of 4
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2015-05-11 14:15:46 +02:00
Bastian Koppelmann 250ef8c768 target-tricore: Fix LOOP using wrong register for compare
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2015-05-11 14:15:46 +02:00
Peter Crosthwaite fee068e4f1 tcg: Delete unused cpu_pc_from_tb()
No code uses the cpu_pc_from_tb() function. Delete from tricore and
arm which each provide an unused implementation. Update the comment
in tcg.h to reflect that this is obsoleted by synchronize_from_tb.

Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2015-04-30 16:06:18 +03:00
Stefan Weil 7b4b0b5795 target-tricore: Fix check which was always false
With a mask value of 0x00400000, the result will never be 1.
This fixes a Coverity warning.

Signed-off-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2015-04-04 09:45:59 +03:00
Bastian Koppelmann f1fdaf5529 target-tricore: fix CACHEA/I_POSTINC/PREINC using data register..
..for address calculation instead address registers.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2015-03-30 13:39:38 +02:00
Bastian Koppelmann f69c24e458 target-tricore: properly fix dvinit_b/h_13
The TriCore documentation was wrong on how to calculate ovf bits for those two
instructions, which I confirmed with real hardware (TC1796 chip). An ovf
actually happens, if the result (without remainder) does not fit into 8/16 bits.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2015-03-24 09:45:28 +01:00
Bastian Koppelmann 00e1754ff1 target-tricore: fix RRPW_DEXTR using wrong reg
RRPW_DEXTR used r1 for the low part and r2 for the high part. It should be the
other way round. This also fixes that the result of the first shift was not
saved in a temp and could overwrite registers that were needed for the second
shift.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2015-03-24 09:45:28 +01:00
Bastian Koppelmann 2b9d09bb3c target-tricore: fix DVINIT_HU/BU calculating overflow before result
dvinit_hu/bu for ISA v1.3 calculate the higher part of the result, that is needed
for the overflow bits, after calculating the overflow bits.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2015-03-24 09:45:28 +01:00
Stefan Weil 30a0d72f94 target-tricore: Fix two helper functions (clang warnings)
clang report:

target-tricore/op_helper.c:1247:24: warning:
  taking the absolute value of unsigned type 'uint32_t' (aka 'unsigned int')
  has no effect [-Wabsolute-value]
target-tricore/op_helper.c:1248:25: warning:
  taking the absolute value of unsigned type 'uint32_t' (aka 'unsigned int')
  has no effect [-Wabsolute-value]
target-tricore/op_helper.c:1249:19: warning:
  taking the absolute value of unsigned type 'uint32_t' (aka 'unsigned int')
  has no effect [-Wabsolute-value]
target-tricore/op_helper.c:1297:24: warning:
  taking the absolute value of unsigned type 'uint32_t' (aka 'unsigned int')
  has no effect [-Wabsolute-value]
target-tricore/op_helper.c:1298:25: warning:
  taking the absolute value of unsigned type 'uint32_t' (aka 'unsigned int')
  has no effect [-Wabsolute-value]
target-tricore/op_helper.c:1299:19: warning:
  taking the absolute value of unsigned type 'uint32_t' (aka 'unsigned int')
  has no effect [-Wabsolute-value]

Fix also the divisor which was taken from the wrong register
(thanks to Peter Maydell for this hint).

Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Message-Id: <1425739412-8144-1-git-send-email-sw@weilnetz.de>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2015-03-24 09:45:28 +01:00
Viswesh de7ad4ce1f Fix typos in comments
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Viswesh <visweshn92@gmail.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2015-03-19 11:30:37 +03:00
Bastian Koppelmann b724b012a4 target-tricore: Add instructions of SYS opcode format
This adds only the non trap instructions.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2015-03-16 15:53:08 +00:00
Bastian Koppelmann eb989d2545 target-tricore: Add instructions of RRRW opcode format
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2015-03-16 15:44:48 +00:00
Bastian Koppelmann 4d108fe33a target-tricore: Add instructions of RRRR opcode format
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2015-03-16 15:44:48 +00:00
Bastian Koppelmann 068fac77c8 target-tricore: Add instructions of RRR1 opcode format, which have 0xe3 as first opcode
Add helpers helper_subadr_h/_ssov which subs one halfword and adds one
halfword, rounds / and saturates each half word independently.

Add microcode helper functions:
    * gen_msubad_h/ads_h: multiply two halfwords left justified and sub from the
                          first one word and add the second one word
                          / and saturate each resulting word independetly.
    * gen_msubadm_h/adms_h: multiply two halfwords in q-format left justified
                            and sub from the first one word and add to
                            the second one word / and saturate each resulting
                            word independetly.
    * gen_msubadr32_h/32s_h: multiply two halfwords in q-format left justified
                             and sub from the first one word and add to
                             the second one word, round both results / and
                             saturate each resulting word independetly.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2015-03-16 15:44:48 +00:00
Bastian Koppelmann 62e47b2e6d target-tricore: Add instructions of RRR1 opcode format, which have 0x63 as first opcode
Add helpers:
    * msub64_q_ssov: multiply two 32 bit q-format number, sub the result from a
                     64 bit q-format number and saturate.
    * msub32_q_sub_ssov: sub two 64 bit q-format numbers and return a 32 bit
                         result.
    * msubr_q_ssov: multiply two 32 bit q-format numbers, sub the result from a 32 bit
                    q-format number and saturate.
    * msubr_q: multiply two 32 bit q-format numbers and sub the result from a 32 bit
               q-format number.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2015-03-16 15:44:48 +00:00
Bastian Koppelmann f4aef476af target-tricore: Add instructions of RRR1 opcode format, which have 0xa3 as first opcode
Add helpers:
    * sub64_ssov: subs two 64 bit values and saturates the result.
    * subr_h/_ssov: subs two halfwords from two words in q-format with rounding
                    / and saturates each result independetly.

Add microcode generator:
    * gen_sub64_d: adds two 64 bit values.
    * gen_msub_h/s_h: multiply four halfwords, sub each result left justfied
                      from two word values / and saturate each result.
    * gen_msubm_h/s_h: multiply four halfwords, sub each result left justfied
                       from two words values in q-format / and saturate each
                       result.
    * gen_msubr32/64_h/s_h: multiply four halfwords, sub each result left
                            justfied from two halftwords/words values in q-format
                            / and saturate each result.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2015-03-16 15:44:48 +00:00
Richard Henderson 42a268c241 tcg: Change translator-side labels to a pointer
This is improved type checking for the translators -- it's no longer
possible to accidentally swap arguments to the branch functions.

Note that the code generating backends still manipulate labels as int.

With notable exceptions, the scope of the change is just a few lines
for each target, so it's not worth building extra machinery to do this
change in per-target increments.

Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Cc: Michael Walle <michael@walle.cc>
Cc: Leon Alrae <leon.alrae@imgtec.com>
Cc: Anthony Green <green@moxielogic.com>
Cc: Jia Liu <proljc@gmail.com>
Cc: Alexander Graf <agraf@suse.de>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Blue Swirl <blauwirbel@gmail.com>
Cc: Guan Xuetao <gxt@mprc.pku.edu.cn>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-03-13 12:28:18 -07:00
Eduardo Habkost 2994fd96d9 cpu: Make cpu_init() return QOM CPUState object
Instead of making cpu_init() return CPUArchState, return CPUState.

Changes were made using the Coccinelle semantic patch below.

  @@
  typedef CPUState;
  identifier e;
  expression args;
  type CPUArchState;
  @@
  -   e =
  +   cpu =
          cpu_init(args);
  -   if (!e) {
  +   if (!cpu) {
          ...
      }
  -   cpu = ENV_GET_CPU(env);
  +   e = cpu->env_ptr;

  @@
  identifier new_env, new_cpu, env, cpu;
  type CPUArchState;
  expression args;
  @@
  -{
  -   CPUState *cpu = ENV_GET_CPU(env);
  -   CPUArchState *new_env = cpu_init(args);
  -   CPUState *new_cpu = ENV_GET_CPU(new_env);
  +{
  +   CPUState *cpu = ENV_GET_CPU(env);
  +   CPUState *new_cpu = cpu_init(args);
  +   CPUArchState *new_env = new_cpu->env_ptr;
      ...
  }

  @@
  identifier c, cpu_init_func, cpu_model;
  type StateType, CPUType;
  @@
  -static inline StateType* cpu_init(const char *cpu_model)
  -{
  -   CPUType *c = cpu_init_func(cpu_model);
  (
  -   if (c == NULL) {
  -       return NULL;
  -   }
  -   return &c->env;
  |
  -   if (c) {
  -       return &c->env;
  -   }
  -   return NULL;
  )
  -}
  +#define cpu_init(cpu_model) CPU(cpu_init_func(cpu_model))

  @@
  identifier cpu_init_func;
  identifier model;
  @@
  -#define cpu_init(model) (&cpu_init_func(model)->env)
  +#define cpu_init(model) CPU(cpu_init_func(model))

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Cc: Blue Swirl <blauwirbel@gmail.com>
Cc: Guan Xuetao <gxt@mprc.pku.edu.cn>
Cc: Riku Voipio <riku.voipio@iki.fi>
Cc: Richard Henderson <rth@twiddle.net>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Michael Walle <michael@walle.cc>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Leon Alrae <leon.alrae@imgtec.com>
Cc: Anthony Green <green@moxielogic.com>
Cc: Jia Liu <proljc@gmail.com>
Cc: Alexander Graf <agraf@suse.de>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Max Filippov <jcmvbkbc@gmail.com>
[AF: Fixed up cpu_copy() manually]
Signed-off-by: Andreas Färber <afaerber@suse.de>
2015-03-10 17:33:51 +01:00
Bastian Koppelmann bebe80fc78 target-tricore: Add instructions of RRR1 opcode format, which have 0xc3 as first opcode
Add helpers helper_addsur_h/_ssov which adds one halfword and subtracts one
halfword, rounds / and saturates each half word independently.

Add microcode helper functions:
    * gen_maddsu_h/sus_h: multiply two halfwords left justified and add to the
                          first one word and subtract from the second one word
                          / and saturate each resulting word independetly.
    * gen_maddsum_h/sums_h: multiply two halfwords in q-format left justified
                            and add to the first one word and subtract from
                            the second one word / and saturate each resulting
                            word independetly.
    * gen_maddsur32_h/32s_h: multiply two halfwords in q-format left justified
                             and add to the first one word and subtract from
                             the second one word, round both results / and
                             saturate each resulting word independetly.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2015-03-03 01:06:00 +00:00
Bastian Koppelmann b00aa8ecbc target-tricore: Add instructions of RRR1 opcode format, which have 0x43 as first opcode
Add helpers:
    * madd64_q_ssov: multiply two 32 bit q-format number, add them with a
                     64 bit q-format number and saturate.
    * madd32_q_add_ssov: add two 64 bit q-format numbers and return a 32 bit
                         result.
    * maddr_q_ssov: multiplay two 32 bit q-format numbers, add a 32 bit
                    q-format number and saturate.
    * maddr_q: multiplay two 32 bit q-format numbers and add a 32 bit
               q-format number.

Note: madd instructions in the q format can behave strange, e.g.
0x1 + (0x80000000 * 0x80000000) << 1 for 32 bit signed values does not cause an
overflow on the guest, because all intermediate results should be handled as if
they are indefinitely precise. We handle this by inverting the overflow bit for
all cases: a + (0x80000000 * 0x80000000) << 1.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2015-03-03 01:05:44 +00:00
Bastian Koppelmann 2e430e1cdc target-tricore: Add instructions of RRR1 opcode format, which have 0x83 as first opcode
Add helpers:
    * add64_ssov: adds two 64 bit values and saturates the result.
    * addr_h/_ssov: adds two halfwords with two words in q-format with rounding
                    / and saturates each result independetly.

Add microcode generator:
    * gen_add64_d: adds two 64 bit values.
    * gen_addsub64_h: adds/subtracts one halfwords with a word and adds/
                      subtracts another halftword with another word.
    * gen_madd_h/s_h: multiply four halfwords, add each result left justfied
                      to two word values / and saturate each result.
    * gen_maddm_h/s_h: multiply four halfwords, add each result left justfied
                       to two words values in q-format / and saturate each
                       result.
    * gen_maddr32/64_h/s_h: multiply four halfwords, add each result left
                            justfied to two halftwords/words values in q-format
                            / and saturate each result.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2015-03-03 01:05:26 +00:00
Bastian Koppelmann 2984cfbdb4 target-tricore: Add instructions of RRR2 opcode format
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2015-03-03 01:05:04 +00:00
Bastian Koppelmann 3debbb5af5 target-tricore: fix msub32_suov return wrong results
If the signed result of the multiplication overflows, we would get a negative
value, which would result in a addition instead of a subtraction.

Now we do the overflow calculation and saturation by hand instead of using
suov32_neg.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2015-03-03 01:04:53 +00:00
Bastian Koppelmann f0cab01b6c target-tricore: Fix RLC_ADDI, RLC_ADDIH using wrong microcode helper
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2015-03-03 01:02:55 +00:00
Richard Henderson fe700adb3d tcg: Introduce tcg_op_buf_count and tcg_op_buf_full
The method by which we count the number of ops emitted
is going to change.  Abstract that away into some inlines.

Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-02-12 21:21:38 -08:00
Richard Henderson 0a7df5da98 tcg: Move emit of INDEX_op_end into gen_tb_end
Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-02-12 21:21:38 -08:00
Bastian Koppelmann 0953225588 target-tricore: Add instructions of RRR opcode format
Add microcode generator function gen_cond_sub.

Add helper functions:
    * ixmax/ixmin: search for the max/min value and its related index in a
                   vector of 16-bit values.
    * pack: dack two data registers into an IEEE-754 single precision floating
            point format number.
    * dvadj: divide-adjust the result after dvstep instructions.
    * dvstep: divide a reg by a divisor, producing 8-bits of quotient at a time.

OPCM_32_RRR_FLOAT -> OPCM_32_RRR_DIVIDE

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2015-01-27 11:48:02 +00:00
Bastian Koppelmann 8fb9d0eb68 target-tricore: Add instructions of RRPW opcode format
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2015-01-27 11:48:02 +00:00
Bastian Koppelmann 12f323e66e target-tricore: Add instructions of RR2 opcode format
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2015-01-27 11:48:02 +00:00
Bastian Koppelmann f1cc6eafdd target-tricore: Add instructions of RR1 opcode format, that have 0x93 as first opcode
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2015-01-27 11:47:51 +00:00
Bastian Koppelmann 85d604af5f target-tricore: split up suov32 into suov32_pos and suov32_neg
suov checks unsigned for an overflow and an underflow, after some arithmetic
operations and saturates the result to either max_uint32 or 0. So far we
handled this by expanding to the next bigger data type and compare whether
the result is > max_uint32 or < 0.

However this approach can fail for an 32 bit multiplication, if both operands of
the multiplication are 0x80000000. This sets the sign bit of the 64 bit integer
and would result in a false saturation to 0.

Since unsigned operations, e.g add, sub, mul always result in either a positive
or negative overflow, we split the functions for suov32 up into two functions
(suov32_pos, suov32_neg) for each case.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2015-01-26 19:56:46 +00:00
Bastian Koppelmann 40a1f64b46 target-tricore: Fix bugs found by coverity
This fixes one bug and one false positive found by coverity. The bug is,
that gen_mtcr was missing a mask to check the flag, which resulted in dead code.

The false positive is a intentional missing break for a jump and link address
insn followed by a jump and link insn. This adds a fall through comment to avoid
the false positive in the future.

Reported-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2015-01-26 19:56:45 +00:00
Bastian Koppelmann 811ea608e9 target-tricore: calculate av bits before saturation
64 bit mac instructions calculated the av bits after the saturation, which
resulted in a wrong PSW. This moves the av bit calculation before the
saturation.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2015-01-26 19:56:45 +00:00
Bastian Koppelmann 5f30046f15 target-tricore: Several translator and cpu model fixes
Fix tc1796 cpu model using wrong ISA version.
Fix cond_add sometimes writing back wrong result.
Fix RCR_SEL and RCR_SELN using wrong registers for result and cond.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2015-01-26 19:56:45 +00:00
Peter Maydell 452e3d49d8 target-tricore: Add missing ULL suffix on 64 bit constant
Add a missing ULL suffix to a 64 bit constant: this suppresses a
compiler warning from mingw32 gcc.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2015-01-26 19:56:45 +00:00
Stefan Weil 37097418be target-tricore: Fix new typos
adress -> address
managment -> management

Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2015-01-15 10:44:13 +03:00
Peter Maydell a4ba200894 More migration fixes and more record/replay preparations. Also moves
the sdhci-pci device id to make space for the rocker device.
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Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging

More migration fixes and more record/replay preparations.  Also moves
the sdhci-pci device id to make space for the rocker device.

# gpg: Signature made Sat 03 Jan 2015 08:22:36 GMT using RSA key ID 78C7AE83
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>"
# gpg:                 aka "Paolo Bonzini <pbonzini@redhat.com>"
# gpg: WARNING: This key is not certified with sufficiently trusted signatures!
# gpg:          It is not certain that the signature belongs to the owner.
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4  E2F7 7E15 100C CD36 69B1
#      Subkey fingerprint: F133 3857 4B66 2389 866C  7682 BFFB D25F 78C7 AE83

* remotes/bonzini/tags/for-upstream:
  pci: move REDHAT_SDHCI device ID to make room for Rocker
  block/iscsi: fix uninitialized variable
  pckbd: set bits 2-3-6-7 of the output port by default
  serial: refine serial_thr_ipending_needed
  gen-icount: check cflags instead of use_icount global
  translate: check cflags instead of use_icount global
  cpu-exec: add a new CF_USE_ICOUNT cflag
  target-ppc: pass DisasContext to SPR generator functions
  atomic: fix position of volatile qualifier

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-01-09 16:29:36 +00:00
Paolo Bonzini cd42d5b236 gen-icount: check cflags instead of use_icount global
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Pavel Dovgalyuk <pavel.dovgaluk@ispras.ru>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-01-03 09:22:12 +01:00
Bastian Koppelmann 9655b9328a target-tricore: Add instructions of RR1 opcode format, that have 0xb3 as first opcode
Add instructions of RR1 opcode format, that have 0xb3 as first opcode.
Add helper functions mulh, mulmh and mulrh, that compute multiplication,
with multiprecision (mulmh) or rounding (mulrh) of 4 halfwords, being either low or high parts
of two 32 bit regs.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-12-21 18:35:49 +00:00
Bastian Koppelmann 436d63ff3e target-tricore: Fix MFCR/MTCR insn and B format offset.
Fix gen_mtcr using wrong register.
Fix gen_mtcr/mfcr using sign extended offsets.
Fix B format insn using not sign extendend offsets.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-12-21 18:35:38 +00:00
Bastian Koppelmann b5fd8fa345 target-tricore: Add missing 1.6 insn of BOL opcode format
Some of the 1.6 ISA instructions were still missing. So let's add them.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-12-21 18:35:28 +00:00
Bastian Koppelmann e2bed107c6 target-tricore: Add instructions of RR opcode format, that have 0x4b as the first opcode
Add instructions of RR opcode format, that have 0x4b as the first opcode.
Add helper functions:
    * parity: Calculates the parity bits for every byte of a 32 int.
    * bmerge/bsplit: Merges two regs into one bitwise/Splits one reg into two bitwise.
    * unpack: unpack a IEEE 754 single precision floating point number as exponent and mantissa.
    * dvinit_b_13/131: (ISA v1.3/v1.31)Prepare operands for a divide operation,
                       where the quotient result is guaranteed to fit into 8 bit.
    * dvinit_h_13/131: (ISA v1.3/v1.31)Prepare operands for a divide operation,
                       where the quotient result is guaranteed to fit into 16 bit.
OPCM_32_RR_FLOAT -> OPCM_32_RR_DIVIDE.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-12-21 18:35:16 +00:00
Bastian Koppelmann f2f1585f60 target-tricore: Add instructions of RR opcode format, that have 0x1 as the first opcode
Add instructions of RR opcode format, that have 0x1 as the first opcode.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-12-21 18:35:00 +00:00
Bastian Koppelmann 0b79a78169 target-tricore: Add instructions of RR opcode format, that have 0xf as the first opcode
Add instructions of RR opcode format, that have 0xf as the first opcode.
Add helper functions:
    * clo/z/s: Counts leading ones/zeros/signs.
    * clo/z/s_h: Count leading ones/zeros/signs in two haflwords.
    * sh/_h: Shifts one/two word/hwords.
    * sha/_h: Shifts one/two word/hwords arithmeticly.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-12-21 18:34:48 +00:00
Bastian Koppelmann d5de7839d7 target-tricore: Add instructions of RR opcode format, that have 0xb as the first opcode
Add instructions of RR opcode format, that have 0xb as the first opcode.
Add helper functions, for hword and byte arithmetics:
    * add_h_ssov/suov: Add two halfword and saturate on overflow.
    * sub_h_ssov/suov: Sub two halfword and saturate on overflow.
    * absdif_h_ssov: Compute absolute difference for halfwords and saturate on overflow.
    * abs_h_ssov/suov: Compute absolute value for two halfwords and saturate on overflow.
    * abs_b/h: Compute absolute value for four/two bytes/halfwords
    * absdif_b/h: Compute absolute difference for four/two bytes/halfwords
    * add_b/h: Add four/two bytes/halfwords.
    * sub_b/h: Sub four/two bytes/halfwords.
    * eq_b/h: Compare four/two bytes/halfwords with four/two bytes/halfwords on
              equality and set all bits of to either one ore zero.
    * eqany_b/h: Compare four/two bytes/halfwords with four/two bytes/halfwords on equality.
    * lt_b/bu/h/hu: Compare four/two bytes/halfwords with four/two bytes/halfwords
                    on less than signed and unsigned.
    * max_b/bu/h/hu: Calculate max for four/two bytes/halfwords signed and unsigned.
    * min_b/bu/h/hu: Calculate min for four/two bytes/halfwords signed and unsigned.
Add helper function abs_ssov, that computes the absolute value for a 32 bit integer and saturates on overflow.
Add microcode generator functions:
    * gen_sub_CC: Caluclates sub and sets the carry bit.
    * gen_subc_CC: Caluclates sub and carry and sets the carry bit
    * gen_abs: Compute absolute value for a 32 bit integer.
    * gen_cond_w: Compares two 32 bit values on cond and sets result either zero or all bits one.

OPC2_32_RR_MIN switched with OPC2_32_RR_MIN_U.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-12-21 18:34:34 +00:00
Bastian Koppelmann e4e3917630 target-tricore: Change SSOV/SUOV makro name to SSOV32/SUOV32
Those makros are exclusively used for 32 bit arithmetics and won't work for
16 bit with two halfwords. So lets get rid of the len parameter and make them
always use 32 bit. Now no token pasting is needed anymore and they can be
regular functions.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-12-21 18:34:22 +00:00
Bastian Koppelmann 7f13420ec0 target-tricore: Fix mask handling JNZ.T being 7 bit long
The mask is actually 7 bit long, instead of 6, so the expression checking
for JNZ.T is always false. Let's make the mask 1 bit wider.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2014-12-21 18:34:05 +00:00
Alex Zuepke 45820fccaf target-tricore: pretty-print register dump and show more status registers
Now using psw_read() to retrieve the status bits correctly.

Signed-off-by: Alex Zuepke <alexander.zuepke@hs-rm.de>
Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2014-12-21 18:33:29 +00:00
Alex Zuepke 4b5b443576 target-tricore: add missing 64-bit MOV in RLC format
Signed-off-by: Alex Zuepke <alexander.zuepke@hs-rm.de>
Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2014-12-21 18:32:27 +00:00
Alex Zuepke af715d9802 target-tricore: typo in BOL format
Signed-off-by: Alex Zuepke <alexander.zuepke@hs-rm.de>
Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2014-12-21 18:32:16 +00:00
Alex Zuepke 781b717c50 target-tricore: fix offset masking in BOL format
Signed-off-by: Alex Zuepke <alexander.zuepke@hs-rm.de>
Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2014-12-21 18:32:03 +00:00
Bastian Koppelmann 328f1f0f08 target-tricore: Add instructions of RCR opcode format
Add instructions of RCR opcode format.
Add helper for madd32/64_ssov and madd32/64_suov.
Add helper for msub32/64_ssov and msub32/64_suov.
Add microcode generator function madd/msub for 32bit and 64bit, which calculate a mul and a add/sub.
OPC2_32_RCR_MSUB_U_32 -> OPC2_32_RCR_MSUB_U_32.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-12-10 11:13:45 +00:00
Bastian Koppelmann 2b2f7d97d8 target-tricore: Add instructions of RLC opcode format
Add instructions of RLC opcode format.
Add helper psw_write/read.
Add microcode generator gen_mtcr/mfcr, which loads/stores a value to a core special function register, which are defined in csfr.def

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-12-10 11:13:45 +00:00
Bastian Koppelmann ed51626066 target-tricore: Add instructions of RCPW, RCRR and RCRW opcode format
Add instructions of RCPW, RCRR and RCRW opcode format.
Add microcode generator function gen_insert.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-12-10 11:13:45 +00:00
Bastian Koppelmann 47e04430ed target-tricore: Make TRICORE_FEATURES implying others.
Since all the TriCore instructionsets are subsets of each other (1.3 C 1.3.1 C 1.6),
make the features implying each other, e.g 1.6 also has 1.3.1 and 1.3. This way
we only need to check our features for the instructionset, where a instruction was first introduced.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-12-10 11:13:45 +00:00
Bastian Koppelmann 0974257ed5 target-tricore: Add instructions of RC opcode format
Add instructions of RC opcode format.
Add helper for mul, sha, absdif with signed saturation on overflow.
Add helper for add, sub, mul with unsigned saturation on overflow.
Add microcode generator functions:
    * gen_add_CC, which calculates the carry bit.
    * gen_addc_CC, which adds the carry bit to the add and calculates the carry bit.
    * gen_absdif, which calculates the absolute difference.
    * gen_mul_i64s/u, which mul two 32 bits val into one 64bit reg.
    * gen_sh_hi, which shifts two 16bit words in one reg.
    * gen_sha_hi, which does a arithmetic shift on two 16bit words.
    * gen_sh_cond, which shifts left a reg by one and writes the result of cond into the lsb.
    * gen_accumulating_cond, which ands/ors/xors the result of cond of the lsbs
      with the lsb of the result.
    * gen_eqany_bi/hi, which checks ever byte/hword on equality.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-12-10 11:13:45 +00:00
Bastian Koppelmann a68e0d547f target-tricore: Add instructions of BRR opcode format
Add instructions of BRR opcode format.
Add MASK_OP_BRR_DISP15_SEXT.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-12-10 11:13:45 +00:00
Bastian Koppelmann 83c1bb1868 target-tricore: Add instructions of BRN opcode format
Add instructions of BRN opcode format.
Add MASK_OP_BRN_DISP15_SEXT.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-12-10 11:13:45 +00:00
Bastian Koppelmann fc2ef4a391 target-tricore: Add instructions of BRC opcode format
Add instructions of BRC opcode format.
Fixed OP2_BRC_JGE -> OP2_32_BRC_JGE

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-12-10 11:13:45 +00:00
Bastian Koppelmann 3fb763cb55 target-tricore: Add instructions of BOL opcode format
Add instructions of BOL opcode format.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-12-10 11:13:44 +00:00
Bastian Koppelmann 3a16ecb063 target-tricore: Add instructions of BO opcode format
Add instructions of BO opcode format.
Add microcode generator functions gen_swap, gen_ldmst.
Add microcode generator functions gen_st/ld_preincr, which write back the address after the memory access.
Add helper for circular and bit reverse addr mode calculation.
Add sign extended bitmask for BO_OFF10 field.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-10-20 12:25:07 +01:00
Bastian Koppelmann b74f2b5bb3 target-tricore: Add instructions of BIT opcode format
Add instructions of BIT opcode format.
Add microcode generator functions gen_bit_1/2op to do 1/2 bit operations on the last bit.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-10-20 12:25:07 +01:00
Bastian Koppelmann f718b0bbfa target-tricore: Add instructions of B opcode format
Add instructions of B opcode format.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-10-20 12:25:07 +01:00
Bastian Koppelmann 59543d4ee1 target-tricore: Add instructions of ABS, ABSB opcode format
Add instructions of ABS, ABSB opcode format.
Add microcode generator functions for ld/st of two 32bit reg as one 64bit value.
Add microcode generator functions for ldmst and swap.
Add helper ldlcx, lducx, stlcx and stucx.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-10-20 12:25:07 +01:00
Bastian Koppelmann 030c58dfb7 target-tricore: Cleanup and Bugfixes
Move FCX loading of save_context_ to caller functions, for STLCX, STUCX insn to use those functions.
Move FCX storing of restore_context_ to caller functions, for LDLCX, LDUCX insn to use those functions.
Remove do_raise_exception function, which caused clang to emit a warning.
Fix: save_context_lower now saves a[11] instead of PSW.
Fix: MASK_OP_ABSB_BPOS starting at wrong offset.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-10-20 12:25:06 +01:00
Richard Henderson dfdb483454 target-tricore: Remove the dummy interrupt boilerplate
It can go back in when it actually does something.

Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-id: 1410626734-3804-18-git-send-email-rth@twiddle.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-25 18:54:22 +01:00
Bastian Koppelmann 44ea34309e target-tricore: Add instructions of SR opcode format
Add instructions of SR opcode format.
Add micro-op generator functions for saturate.
Add helper return from exception (rfe).

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-id: 1409572800-4116-16-git-send-email-kbastian@mail.uni-paderborn.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-01 14:49:21 +01:00
Bastian Koppelmann 5a7634a28c target-tricore: Add instructions of SLR, SSRO and SRO opcode format
Add instructions of SLR, SSRO and SRO opcode format.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>

Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1409572800-4116-15-git-send-email-kbastian@mail.uni-paderborn.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-01 14:49:21 +01:00
Bastian Koppelmann 5de93515f9 target-tricore: Add instructions of SC opcode format
Add instructions of SC opcode format.
Add helper for begin interrupt service routine.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-id: 1409572800-4116-14-git-send-email-kbastian@mail.uni-paderborn.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-01 14:49:21 +01:00
Bastian Koppelmann a47b50db60 target-tricore: Add instructions of SBR opcode format
Add instructions of SBR opcode format.
Add gen_loop micro-op generator function.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>

Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1409572800-4116-13-git-send-email-kbastian@mail.uni-paderborn.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-01 14:49:21 +01:00
Bastian Koppelmann 70b0226250 target-tricore: Add instructions of SBC and SBRN opcode format
Add instructions of SBC and SBRN opcode format.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>

Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1409572800-4116-12-git-send-email-kbastian@mail.uni-paderborn.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-01 14:49:21 +01:00
Bastian Koppelmann 9a31922b08 target-tricore: Add instructions of SB opcode format
Add instructions of SB opcode format.
Add helper call/ret.
Add micro-op generator functions for branches.
Add makro to generate helper functions.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-id: 1409572800-4116-11-git-send-email-kbastian@mail.uni-paderborn.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-01 14:49:21 +01:00
Bastian Koppelmann d279821074 target-tricore: Add instructions of SRRS and SLRO opcode format
Add instructions of SSRS and SLRO opcode format.
Add micro-op generator functions for offset loads.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>

Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1409572800-4116-10-git-send-email-kbastian@mail.uni-paderborn.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-01 14:49:21 +01:00
Bastian Koppelmann 46aa848ffb target-tricore: Add instructions of SSR opcode format
Add instructions of SSR opcode format.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>

Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1409572800-4116-9-git-send-email-kbastian@mail.uni-paderborn.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-01 14:49:21 +01:00
Bastian Koppelmann 2692802a37 target-tricore: Add instructions of SRR opcode format
Add instructions of SRR opcode format.
Add helper for add/sub_ssov.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-id: 1409572800-4116-8-git-send-email-kbastian@mail.uni-paderborn.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-01 14:49:21 +01:00
Bastian Koppelmann 0707ec1bea target-tricore: Add instructions of SRC opcode format
Add instructions of SRC opcode format.
Add micro-op generator functions for add, conditional add/sub and shi/shai.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>

Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1409572800-4116-7-git-send-email-kbastian@mail.uni-paderborn.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-01 14:49:20 +01:00
Bastian Koppelmann 7c87d074d2 target-tricore: Add masks and opcodes for decoding
Add masks and opcodes for decoding TriCore instructions.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>

Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1409572800-4116-6-git-send-email-kbastian@mail.uni-paderborn.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-01 14:49:20 +01:00
Bastian Koppelmann 0aaeb118b3 target-tricore: Add initialization for translation and activate target
Add tcg and cpu model initialization.
Add gen_intermediate_code function.
Activate target in configure and add softmmu config.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-id: 1409572800-4116-5-git-send-email-kbastian@mail.uni-paderborn.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-01 14:49:20 +01:00
Bastian Koppelmann 2d30267e8e target-tricore: Add softmmu support
Add basic softmmu support for TriCore

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-id: 1409572800-4116-4-git-send-email-kbastian@mail.uni-paderborn.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-01 14:49:20 +01:00
Bastian Koppelmann 48e06fe0ed target-tricore: Add target stubs and qom-cpu
Add TriCore target stubs, and QOM cpu, and Maintainer

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-id: 1409572800-4116-2-git-send-email-kbastian@mail.uni-paderborn.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-01 14:49:20 +01:00