b01932889d
1249 Commits
| Author | SHA1 | Message | Date | |
|---|---|---|---|---|
Daniel P. Berrangé
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b01932889d |
qtest: use correct boolean type for failover property
QMP device_add does not historically validate the parameter types. At some point it will likely change to enforce correct types, to match behaviour of -device. The failover property is expected to be a boolean in JSON. Signed-off-by: "Daniel P. Berrangé" <berrange@redhat.com> Message-ID: <20240103123005.2400437-1-berrange@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Thomas Huth <thuth@redhat.com> |
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Peter Maydell
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c8193acc07 |
migration 1st pull for 9.0
- We lost Juan and Leo in the maintainers file - Steven's suspend state fix - Steven's fix for coverity on migrate_mode - Avihai's migration cleanup series -----BEGIN PGP SIGNATURE----- iIgEABYKADAWIQS5GE3CDMRX2s990ak7X8zN86vXBgUCZZY0TxIccGV0ZXJ4QHJl ZGhhdC5jb20ACgkQO1/MzfOr1wbSxgEAoM5g3wkc22lpAlRpU+hJUqT9NVOVQSK+ Fk7XJYTdSgABAKzykA6hAmU5Kj+yVI6jI874SVZbs2FWpFs4osvsKk4D =sfuM -----END PGP SIGNATURE----- Merge tag 'migration-20240104-pull-request' of https://gitlab.com/peterx/qemu into staging migration 1st pull for 9.0 - We lost Juan and Leo in the maintainers file - Steven's suspend state fix - Steven's fix for coverity on migrate_mode - Avihai's migration cleanup series # -----BEGIN PGP SIGNATURE----- # # iIgEABYKADAWIQS5GE3CDMRX2s990ak7X8zN86vXBgUCZZY0TxIccGV0ZXJ4QHJl # ZGhhdC5jb20ACgkQO1/MzfOr1wbSxgEAoM5g3wkc22lpAlRpU+hJUqT9NVOVQSK+ # Fk7XJYTdSgABAKzykA6hAmU5Kj+yVI6jI874SVZbs2FWpFs4osvsKk4D # =sfuM # -----END PGP SIGNATURE----- # gpg: Signature made Thu 04 Jan 2024 04:30:07 GMT # gpg: using EDDSA key B9184DC20CC457DACF7DD1A93B5FCCCDF3ABD706 # gpg: issuer "peterx@redhat.com" # gpg: Good signature from "Peter Xu <xzpeter@gmail.com>" [unknown] # gpg: aka "Peter Xu <peterx@redhat.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: B918 4DC2 0CC4 57DA CF7D D1A9 3B5F CCCD F3AB D706 * tag 'migration-20240104-pull-request' of https://gitlab.com/peterx/qemu: (26 commits) migration: fix coverity migrate_mode finding migration/multifd: Remove unnecessary usage of local Error migration: Remove unnecessary usage of local Error migration: Fix migration_channel_read_peek() error path migration/multifd: Remove error_setg() in migration_ioc_process_incoming() migration/multifd: Fix leaking of Error in TLS error flow migration/multifd: Simplify multifd_channel_connect() if else statement migration/multifd: Fix error message in multifd_recv_initial_packet() migration: Remove errp parameter in migration_fd_process_incoming() migration: Refactor migration_incoming_setup() migration: Remove nulling of hostname in migrate_init() migration: Remove migrate_max_downtime() declaration tests/qtest: postcopy migration with suspend tests/qtest: precopy migration with suspend tests/qtest: option to suspend during migration tests/qtest: migration events migration: preserve suspended for bg_migration migration: preserve suspended for snapshot migration: preserve suspended runstate migration: propagate suspended runstate ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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Peter Maydell
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05470c3979 |
* configure: use a native non-cross compiler for linux-user
* meson: cleanups * target/i386: miscellaneous cleanups and optimizations * target/i386: implement CMPccXADD * target/i386: the sgx_epc_get_section stub is reachable * esp: check for NULL result from scsi_device_find() -----BEGIN PGP SIGNATURE----- iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmWRImYUHHBib256aW5p QHJlZGhhdC5jb20ACgkQv/vSX3jHroNd7AgAgcyJGiMfUkXqhefplpm06RDXQIa8 FuoJqPb21lO75DQKfaFRAc4xGLagjJROMJGHMm9HvMu2VlwvOydkQlfFRspENxQ/ 5XzGdb/X0A7HA/mwUfnMB1AZx0Vs32VI5IBSc6acc9fmgeZ84XQEoM3KBQHUik7X mSkE4eltR9gJ+4IaGo4voZtK+YoVD8nEcuqmnKihSPWizev0FsZ49aNMtaYa9qC/ Xs3kiQd/zPibHDHJu0ulFsNZgxtUcvlLHTCf8gO4dHWxCFLXGubMush83McpRtNB Qoh6cTLH+PBXfrxMR3zmTZMNvo8Euls3s07Y8TkNP4vdIIE/kMeMDW1wJw== =mq30 -----END PGP SIGNATURE----- Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging * configure: use a native non-cross compiler for linux-user * meson: cleanups * target/i386: miscellaneous cleanups and optimizations * target/i386: implement CMPccXADD * target/i386: the sgx_epc_get_section stub is reachable * esp: check for NULL result from scsi_device_find() # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmWRImYUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroNd7AgAgcyJGiMfUkXqhefplpm06RDXQIa8 # FuoJqPb21lO75DQKfaFRAc4xGLagjJROMJGHMm9HvMu2VlwvOydkQlfFRspENxQ/ # 5XzGdb/X0A7HA/mwUfnMB1AZx0Vs32VI5IBSc6acc9fmgeZ84XQEoM3KBQHUik7X # mSkE4eltR9gJ+4IaGo4voZtK+YoVD8nEcuqmnKihSPWizev0FsZ49aNMtaYa9qC/ # Xs3kiQd/zPibHDHJu0ulFsNZgxtUcvlLHTCf8gO4dHWxCFLXGubMush83McpRtNB # Qoh6cTLH+PBXfrxMR3zmTZMNvo8Euls3s07Y8TkNP4vdIIE/kMeMDW1wJw== # =mq30 # -----END PGP SIGNATURE----- # gpg: Signature made Sun 31 Dec 2023 08:12:22 GMT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (46 commits) meson.build: report graphics backends separately configure, meson: rename targetos to host_os meson: rename config_all meson: remove CONFIG_ALL meson: remove config_targetos meson: remove CONFIG_POSIX and CONFIG_WIN32 from config_targetos meson: remove OS definitions from config_targetos meson: always probe u2f and canokey if the option is enabled meson: move subdirs to "Collect sources" section meson: move config-host.h definitions together meson: move CFI detection code with other compiler flags meson: keep subprojects together meson: move accelerator dependency checks together meson: move option validation together meson: move program checks together meson: add more sections to main meson.build configure: unify again the case arms in probe_target_compiler configure: remove unnecessary subshell Makefile: clean qemu-iotests output meson: use version_compare() to compare version ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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Steve Sistare
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2b58a8b963 |
tests/qtest: postcopy migration with suspend
Add a test case to verify that the suspended state is handled correctly by live migration postcopy. The test suspends the src, migrates, then wakes the dest. Signed-off-by: Steve Sistare <steven.sistare@oracle.com> Reviewed-by: Peter Xu <peterx@redhat.com> Link: https://lore.kernel.org/r/1704312341-66640-13-git-send-email-steven.sistare@oracle.com Signed-off-by: Peter Xu <peterx@redhat.com> |
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Steve Sistare
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b1fdd21e8c |
tests/qtest: precopy migration with suspend
Add a test case to verify that the suspended state is handled correctly during live migration precopy. The test suspends the src, migrates, then wakes the dest. Signed-off-by: Steve Sistare <steven.sistare@oracle.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Peter Xu <peterx@redhat.com> Link: https://lore.kernel.org/r/1704312341-66640-12-git-send-email-steven.sistare@oracle.com Signed-off-by: Peter Xu <peterx@redhat.com> |
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Steve Sistare
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5014478e0d |
tests/qtest: option to suspend during migration
Add an option to suspend the src in a-b-bootblock.S, which puts the guest in S3 state after one round of writing to memory. The option is enabled by poking a 1 into the suspend_me word in the boot block prior to starting the src vm. Generate symbol offsets in a-b-bootblock.h so that the suspend_me offset is known. Generate the bootblock for each test, because suspend_me may differ for each. Signed-off-by: Steve Sistare <steven.sistare@oracle.com> Acked-by: Peter Xu <peterx@redhat.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Link: https://lore.kernel.org/r/1704312341-66640-11-git-send-email-steven.sistare@oracle.com Signed-off-by: Peter Xu <peterx@redhat.com> |
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Steve Sistare
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f0649758be |
tests/qtest: migration events
Define a state object to capture events seen by migration tests, to allow more events to be captured in a subsequent patch, and simplify event checking in wait_for_migration_pass. No functional change. Signed-off-by: Steve Sistare <steven.sistare@oracle.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: "Daniel P. Berrangé" <berrange@redhat.com> Link: https://lore.kernel.org/r/1704312341-66640-10-git-send-email-steven.sistare@oracle.com Signed-off-by: Peter Xu <peterx@redhat.com> |
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Paolo Bonzini
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d0cda6f461 |
configure, meson: rename targetos to host_os
This variable is about the host OS, not the target. It is used a lot more since the Meson conversion, but the original sin dates back to 2003. Time to fix it. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> |
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Paolo Bonzini
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cfc1a889e5 |
meson: rename config_all
config_all now lists only accelerators, rename it to indicate its actual content. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> |
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Paolo Bonzini
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1220f5813a |
meson: remove config_targetos
config_targetos is now empty and can be removed; its use in sourcesets that do not involve target-specific files can be replaced with an empty dictionary. In fact, at this point *all* sourcesets that do not involve target-specific files are just glorified mutable arrays. Enforce that they never test for symbols in "when:" by computing the set of files without "strict: false". Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> |
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Zhao Liu
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c40db4ba60 |
tests: bios-tables-test: Rename smbios type 4 related test functions
In fact, type4-count, core-count, core-count2, thread-count and thread-count2 are tested with KVM not TCG. Rename these test functions to reflect KVM base instead of TCG. Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20231127160202.1037290-1-zhao1.liu@linux.intel.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> |
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Thomas Huth
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71dc6ca2a8 |
tests/qtest/npcm7xx_pwm-test: Only do full testing in slow mode
The npcm7xx_pwm-test can take quite a while when running with --enable-debug on a loaded system. The tests here are quite repetitive - by default it should be fine if we only execute some of them and only execute all when running in slow testing mode. Message-ID: <20231215143524.49241-1-thuth@redhat.com> Reviewed-by: "Daniel P. Berrangé" <berrange@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com> |
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Thomas Huth
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81c2c9dd5d |
tests/qtest/migration-test: Fix analyze-migration.py for s390x
The migration stream on s390x contains data for the storage_attributes which the analyze-migration.py cannot handle yet. Add the basic code for handling this, so we can re-enable the check in the migration-test. Message-ID: <20231120113951.162090-1-thuth@redhat.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Signed-off-by: Thomas Huth <thuth@redhat.com> |
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Stefan Hajnoczi
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169c4e7764 |
* Fix wording in iotest 149
* Fix whitespace issues in sh4 code (ignore checkpatch.pl warnings here) * Make sure to check return values in qtests -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmVt4PwRHHRodXRoQHJl ZGhhdC5jb20ACgkQLtnXdP5wLbWhYxAAm6ww++qfCh5uLrKjXrv/ZS+b+8UVMT+p wOBNBz0RDpDahAwesxLABAg9b+fabLTx9OpOyQRgmM/ofCoW/Oi7xzCEwv9JPJX0 Kr7x5AMCTc2hPydxsMenWYZXLZXcc0HSkB+4yN5FTeOl8YPoRetegsGbiirGpod1 QyD/oLMZzBxqteF/m0a4gxEuwi3qgRVIOkdk8zeSBMAl6EUazsKR8sTrdCrkupHl ddMKjRH4Gr2sXoZ8L/mr4T5FodVxAF1pcZnVyPYDlVgNK/V0IWDcbmFFNr0rXxCM CZz7gIOZkpm/MXpVE9UEg++ZOQ16gDUNpvQRyNPgIn0vbiuF5kcXmUpstJWHDico O98wgH6im3iC7xyaMTOq3pjSb9RNP4cmIw77EKJyS93RDAgiCX0ozN3zEkxsvZYu hQadBd3TSUP6jxz2SWQ6irCwkElfozCc1cPfUyW0rFXjLqWei0UirWDdyN5dL8vk pkupZG5p3jiiZs1hm+TQ4W1CPVZFTAW+LcI7V/Na3EBKQvrjYDlHMQdx0NaJh5e3 xn84bvTnuYfT/I63z9zqIbMwPQ5t+lJaR9ohkn9Q4tTEnHuMV9svON5rsRc3YE6p XrR02G9zu4kVAKs51DFNWC9SLgviW+LB2DCe+e2CrqwPjiz+MeOVGEEre7/nnj/q clP7u3MyX5A= =rU6S -----END PGP SIGNATURE----- Merge tag 'pull-request-2023-12-04' of https://gitlab.com/thuth/qemu into staging * Fix wording in iotest 149 * Fix whitespace issues in sh4 code (ignore checkpatch.pl warnings here) * Make sure to check return values in qtests # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmVt4PwRHHRodXRoQHJl # ZGhhdC5jb20ACgkQLtnXdP5wLbWhYxAAm6ww++qfCh5uLrKjXrv/ZS+b+8UVMT+p # wOBNBz0RDpDahAwesxLABAg9b+fabLTx9OpOyQRgmM/ofCoW/Oi7xzCEwv9JPJX0 # Kr7x5AMCTc2hPydxsMenWYZXLZXcc0HSkB+4yN5FTeOl8YPoRetegsGbiirGpod1 # QyD/oLMZzBxqteF/m0a4gxEuwi3qgRVIOkdk8zeSBMAl6EUazsKR8sTrdCrkupHl # ddMKjRH4Gr2sXoZ8L/mr4T5FodVxAF1pcZnVyPYDlVgNK/V0IWDcbmFFNr0rXxCM # CZz7gIOZkpm/MXpVE9UEg++ZOQ16gDUNpvQRyNPgIn0vbiuF5kcXmUpstJWHDico # O98wgH6im3iC7xyaMTOq3pjSb9RNP4cmIw77EKJyS93RDAgiCX0ozN3zEkxsvZYu # hQadBd3TSUP6jxz2SWQ6irCwkElfozCc1cPfUyW0rFXjLqWei0UirWDdyN5dL8vk # pkupZG5p3jiiZs1hm+TQ4W1CPVZFTAW+LcI7V/Na3EBKQvrjYDlHMQdx0NaJh5e3 # xn84bvTnuYfT/I63z9zqIbMwPQ5t+lJaR9ohkn9Q4tTEnHuMV9svON5rsRc3YE6p # XrR02G9zu4kVAKs51DFNWC9SLgviW+LB2DCe+e2CrqwPjiz+MeOVGEEre7/nnj/q # clP7u3MyX5A= # =rU6S # -----END PGP SIGNATURE----- # gpg: Signature made Mon 04 Dec 2023 09:23:56 EST # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * tag 'pull-request-2023-12-04' of https://gitlab.com/thuth/qemu: tests/qtest: check the return value sh4: Coding style: Remove tabs tests/qemu-iotests/149: Use more inclusive language in this test Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> |
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Zhu Jun
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4d98618b8a |
tests/qtest: check the return value
These variables "ret" are never referenced in the code, thus add check logic for the "ret" Signed-off-by: Zhu Jun <zhujun2@cmss.chinamobile.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20231121080802.4500-1-zhujun2@cmss.chinamobile.com> Signed-off-by: Thomas Huth <thuth@redhat.com> |
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Ani Sinha
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de35244e99 |
tests/acpi/bios-tables-test: do not write new blobs unless there are changes
When dumping table blobs using rebuild-expected-aml.sh, table blobs from all test variants are dumped regardless of whether there are any actual changes to the tables or not. This creates lot of new files for various test variants that are not part of the git repository. This is because we do not check in all table blobs for all test variants into the repository. Only those blobs for those variants that are different from the generic test-variant agnostic blob are checked in. This change makes the test smarter by checking if at all there are any changes in the tables from the checked-in gold master blobs and take actions accordingly. When there are no changes: - No new table blobs would be written. - Existing table blobs will be refreshed (git diff will show no changes). When there are changes: - New table blob files will be dumped. - Existing table blobs will be refreshed (git diff will show that the files changed, asl diff will show the actual changes). When new tables are introduced: - Zero byte empty file blobs for new tables as instructed in the header of bios-tables-test.c will be regenerated to actual table blobs. This would make analyzing changes to tables less confusing and there would be no need to clean useless untracked files when there are no table changes. CC: peter.maydell@linaro.org Signed-off-by: Ani Sinha <anisinha@redhat.com> Message-Id: <20231107044952.5461-1-anisinha@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Acked-by: Igor Mammedov <imammedo@redhat.com> |
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Michael S. Tsirkin
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cadfc72939 |
netdev: set timeout depending on loadavg
netdev test keeps failing sometimes. I don't think we should increase the timeout some more: let's try something else instead, testing how busy the system is. Seems to work for me. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> |
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Michael Tokarev
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4b3e4d2b43 |
tests/qtest/ufs-test.c: spelling fix: tranfer
Fixes:
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Michael Tokarev
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8053feaae0 |
tests/qtest/migration-test.c: spelling fix: bandwith
Fixes:
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Stefan Hajnoczi
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ed1d873caa |
Misc hardware patch queue
HW emulation: - PMBus fixes and tests (Titus) - IDE fixes and tests (Fiona) - New ADM1266 sensor (Titus) - Better error propagation in PCI-ISA i82378 (Philippe) - Declare SD model QOM types using DEFINE_TYPES macro (Philippe) Topology: - Fix CPUState::nr_cores calculation (Zhuocheng Ding and Zhao Liu) Monitor: - Synchronize CPU state in 'info lapic' (Dongli Zhang) QOM: - Have 'cpu-qom.h' target-agnostic (Philippe) - Move ArchCPUClass definition to each target's cpu.h (Philippe) - Call object_class_is_abstract once in cpu_class_by_name (Philippe) UI: - Use correct key names in titles on MacOS / SDL2 (Adrian) MIPS: - Fix MSA BZ/BNZ and TX79 LQ/SQ opcodes (Philippe) Nios2: - Create IRQs *after* vCPU is realized (Philippe) PPC: - Restrict KVM objects to system emulation (Philippe) - Move target-specific definitions out of 'cpu-qom.h' (Philippe) S390X: - Make hw/s390x/css.h and hw/s390x/sclp.h headers target agnostic (Philippe) X86: - HVF & KVM cleanups (Philippe) Various targets: - Use env_archcpu() to optimize (Philippe) Misc: - Few global variable shadowing removed (Philippe) - Introduce cpu_exec_reset_hold and factor tcg_cpu_reset_hold out (Philippe) - Remove few more 'softmmu' mentions (Philippe) - Fix and cleanup in vl.c (Akihiko & Marc-André) - Resource leak fix in dump (Zongmin Zhou) - MAINTAINERS updates (Thomas, Daniel) -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmVKKmEACgkQ4+MsLN6t wN4xHQ//X/enH4C7K3VP/tSinDiwmXN2o61L9rjqSDQkBaCtktZx4c8qKSDL7V4S vwzmvvBn3biMXQwZNVJo9d0oz2qoaF9tI6Ao0XDHAan9ziagfG9YMqWhkCfj077Q jLdCqkUuMJBvQgXGB1a6UgCme8PQx7h0oqjbCNfB0ZBls24b5DiEjO87LE4OTbTi zKRhYEpZpGwIVcy+1dAsbaBpGFP06sr1doB9Wz4c06eSx7t0kFSPk6U4CyOPrGXh ynyCxPwngxIXmarY8gqPs3SBs7oXsH8Q/ZOHr1LbuXhwSuw/0zBQU9aF7Ir8RPan DB79JjPrtxTAhICKredWT79v9M18D2/1MpONgg4vtx5K2FzGYoAJULCHyfkHMRSM L6/H0ZQPHvf7w72k9EcSQIhd0wPlMqRmfy37/8xcLiw1h4l/USx48QeKaeFWeSEu DgwSk+R61HbrKvQz/U0tF98zUEyBaQXNrKmyzht0YE4peAtpbPNBeRHkd0GMae/Z HOmkt8QlFQ0T14qSK7mSHaSJTUzRvFGD01cbuCDxVsyCWWsesEikXBACZLG5RCRY Rn1WeX1H9eE3kKi9iueLnhzcF9yM5XqFE3f6RnDzY8nkg91lsTMSQgFcIpv6uGyp 3WOTNSC9SoFyI3x8pCWiKOGytPUb8xk+PnOA85wYvVmT+7j6wus= =OVdQ -----END PGP SIGNATURE----- Merge tag 'misc-cpus-20231107' of https://github.com/philmd/qemu into staging Misc hardware patch queue HW emulation: - PMBus fixes and tests (Titus) - IDE fixes and tests (Fiona) - New ADM1266 sensor (Titus) - Better error propagation in PCI-ISA i82378 (Philippe) - Declare SD model QOM types using DEFINE_TYPES macro (Philippe) Topology: - Fix CPUState::nr_cores calculation (Zhuocheng Ding and Zhao Liu) Monitor: - Synchronize CPU state in 'info lapic' (Dongli Zhang) QOM: - Have 'cpu-qom.h' target-agnostic (Philippe) - Move ArchCPUClass definition to each target's cpu.h (Philippe) - Call object_class_is_abstract once in cpu_class_by_name (Philippe) UI: - Use correct key names in titles on MacOS / SDL2 (Adrian) MIPS: - Fix MSA BZ/BNZ and TX79 LQ/SQ opcodes (Philippe) Nios2: - Create IRQs *after* vCPU is realized (Philippe) PPC: - Restrict KVM objects to system emulation (Philippe) - Move target-specific definitions out of 'cpu-qom.h' (Philippe) S390X: - Make hw/s390x/css.h and hw/s390x/sclp.h headers target agnostic (Philippe) X86: - HVF & KVM cleanups (Philippe) Various targets: - Use env_archcpu() to optimize (Philippe) Misc: - Few global variable shadowing removed (Philippe) - Introduce cpu_exec_reset_hold and factor tcg_cpu_reset_hold out (Philippe) - Remove few more 'softmmu' mentions (Philippe) - Fix and cleanup in vl.c (Akihiko & Marc-André) - Resource leak fix in dump (Zongmin Zhou) - MAINTAINERS updates (Thomas, Daniel) # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmVKKmEACgkQ4+MsLN6t # wN4xHQ//X/enH4C7K3VP/tSinDiwmXN2o61L9rjqSDQkBaCtktZx4c8qKSDL7V4S # vwzmvvBn3biMXQwZNVJo9d0oz2qoaF9tI6Ao0XDHAan9ziagfG9YMqWhkCfj077Q # jLdCqkUuMJBvQgXGB1a6UgCme8PQx7h0oqjbCNfB0ZBls24b5DiEjO87LE4OTbTi # zKRhYEpZpGwIVcy+1dAsbaBpGFP06sr1doB9Wz4c06eSx7t0kFSPk6U4CyOPrGXh # ynyCxPwngxIXmarY8gqPs3SBs7oXsH8Q/ZOHr1LbuXhwSuw/0zBQU9aF7Ir8RPan # DB79JjPrtxTAhICKredWT79v9M18D2/1MpONgg4vtx5K2FzGYoAJULCHyfkHMRSM # L6/H0ZQPHvf7w72k9EcSQIhd0wPlMqRmfy37/8xcLiw1h4l/USx48QeKaeFWeSEu # DgwSk+R61HbrKvQz/U0tF98zUEyBaQXNrKmyzht0YE4peAtpbPNBeRHkd0GMae/Z # HOmkt8QlFQ0T14qSK7mSHaSJTUzRvFGD01cbuCDxVsyCWWsesEikXBACZLG5RCRY # Rn1WeX1H9eE3kKi9iueLnhzcF9yM5XqFE3f6RnDzY8nkg91lsTMSQgFcIpv6uGyp # 3WOTNSC9SoFyI3x8pCWiKOGytPUb8xk+PnOA85wYvVmT+7j6wus= # =OVdQ # -----END PGP SIGNATURE----- # gpg: Signature made Tue 07 Nov 2023 20:15:29 HKT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'misc-cpus-20231107' of https://github.com/philmd/qemu: (75 commits) dump: Add close fd on error return to avoid resource leak ui/sdl2: use correct key names in win title on mac MAINTAINERS: Add more guest-agent related files to the corresponding section MAINTAINERS: Add include/hw/xtensa/mx_pic.h to the XTFPGA machine section MAINTAINERS: update libvirt devel mailing list address MAINTAINERS: Add the CAN documentation file to the CAN section MAINTAINERS: Add include/hw/timer/tmu012.h to the SH4 R2D section hw/sd: Declare QOM types using DEFINE_TYPES() macro hw/i2c: pmbus: reset page register for out of range reads hw/i2c: pmbus: immediately clear faults on request tests/qtest: add tests for ADM1266 hw/sensor: add ADM1266 device model hw/i2c: pmbus: add VCAP register hw/i2c: pmbus: add fan support hw/i2c: pmbus: add vout mode bitfields hw/i2c: pmbus add support for block receive tests/qtest: ahci-test: add test exposing reset issue with pending callback hw/ide: reset: cancel async DMA operation before resetting state hw/cpu: Update the comments of nr_cores and nr_dies system/cpus: Fix CPUState.nr_cores' calculation ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> |
||
|
Titus Rwantare
|
ff0511282d |
hw/i2c: pmbus: reset page register for out of range reads
The linux pmbus driver scans all possible pages and does not reset the current page after the scan, making all future page reads fail as out of range on devices with a single page. This change resets out of range pages immediately on write. Also added a qtest for simultaneous writes to all pages. Reviewed-by: Hao Wu <wuhaotsh@google.com> Signed-off-by: Titus Rwantare <titusr@google.com> Message-ID: <20231023-staging-pmbus-v3-v4-8-07a8cb7cd20a@google.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
||
|
Titus Rwantare
|
5861f5abf4 |
tests/qtest: add tests for ADM1266
The ADM1266 can have string fields written by the driver, so it's worth specifically testing. Reviewed-by: Hao Wu <wuhaotsh@google.com> Acked-by: Corey Minyard <cminyard@mvista.com> Signed-off-by: Titus Rwantare <titusr@google.com> [PMD: Cover file in MAINTAINERS] Message-ID: <20231023-staging-pmbus-v3-v4-6-07a8cb7cd20a@google.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
||
|
Fiona Ebner
|
cc610857bb |
tests/qtest: ahci-test: add test exposing reset issue with pending callback
Before commit "hw/ide: reset: cancel async DMA operation before resetting state", this test would fail, because a reset with a pending write operation would lead to an unsolicited write to the first sector of the disk. The test writes a pattern to the beginning of the disk and verifies that it is still intact after a reset with a pending operation. It also checks that the pending operation actually completes correctly. Signed-off-by: Fiona Ebner <f.ebner@proxmox.com> Message-ID: <20230906130922.142845-2-f.ebner@proxmox.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
||
|
Stefan Hajnoczi
|
f6b615b52d |
virtio,pc,pci: features, fixes
virtio sound card support
vhost-user: back-end state migration
cxl:
line length reduction
enabling fabric management
vhost-vdpa:
shadow virtqueue hash calculation Support
shadow virtqueue RSS Support
tests:
CPU topology related smbios test cases
Fixes, cleanups all over the place
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging
virtio,pc,pci: features, fixes
virtio sound card support
vhost-user: back-end state migration
cxl:
line length reduction
enabling fabric management
vhost-vdpa:
shadow virtqueue hash calculation Support
shadow virtqueue RSS Support
tests:
CPU topology related smbios test cases
Fixes, cleanups all over the place
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
# -----BEGIN PGP SIGNATURE-----
#
# iQFDBAABCAAtFiEEXQn9CHHI+FuUyooNKB8NuNKNVGkFAmVKDDoPHG1zdEByZWRo
# YXQuY29tAAoJECgfDbjSjVRpF08H/0Zts8uvkHbgiOEJw4JMHU6/VaCipfIYsp01
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# 0w4IXEJPBgZYbX9oc6zvTQnbLDBJbDU89mnme0TcmNMKWmQKTtc=
# =vEv+
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 07 Nov 2023 18:06:50 HKT
# gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469
# gpg: issuer "mst@redhat.com"
# gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full]
# gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full]
# Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67
# Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469
* tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (63 commits)
acpi/tests/avocado/bits: enable console logging from bits VM
acpi/tests/avocado/bits: enforce 32-bit SMBIOS entry point
hw/cxl: Add tunneled command support to mailbox for switch cci.
hw/cxl: Add dummy security state get
hw/cxl/type3: Cleanup multiple CXL_TYPE3() calls in read/write functions
hw/cxl/mbox: Add Get Background Operation Status Command
hw/cxl: Add support for device sanitation
hw/cxl/mbox: Wire up interrupts for background completion
hw/cxl/mbox: Add support for background operations
hw/cxl: Implement Physical Ports status retrieval
hw/pci-bridge/cxl_downstream: Set default link width and link speed
hw/cxl/mbox: Add Physical Switch Identify command.
hw/cxl/mbox: Add Information and Status / Identify command
hw/cxl: Add a switch mailbox CCI function
hw/pci-bridge/cxl_upstream: Move defintion of device to header.
hw/cxl/mbox: Generalize the CCI command processing
hw/cxl/mbox: Pull the CCI definition out of the CXLDeviceState
hw/cxl/mbox: Split mailbox command payload into separate input and output
hw/cxl/mbox: Pull the payload out of struct cxl_cmd and make instances constant
hw/cxl: Fix a QEMU_BUILD_BUG_ON() in switch statement scope issue.
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
|
||
|
Zhao Liu
|
f58db4eeb1 |
tests: bios-tables-test: Add ACPI table binaries for smbios type4 thread count2 test
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 5 and 6.
Changes in the tables:
FACP:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly of /tmp/aml-CNE3C2, Mon Oct 23 15:25:01 2023
+ *
+ * ACPI Data Table [FACP]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)]
+[004h 0004 4] Table Length : 000000F4
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : B3
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] FACS Address : 00000000
+[028h 0040 4] DSDT Address : 00000000
+[02Ch 0044 1] Model : 01
+[02Dh 0045 1] PM Profile : 00 [Unspecified]
+[02Eh 0046 2] SCI Interrupt : 0009
+[030h 0048 4] SMI Command Port : 000000B2
+[034h 0052 1] ACPI Enable Value : 02
+[035h 0053 1] ACPI Disable Value : 03
+[036h 0054 1] S4BIOS Command : 00
+[037h 0055 1] P-State Control : 00
+[038h 0056 4] PM1A Event Block Address : 00000600
+[03Ch 0060 4] PM1B Event Block Address : 00000000
+[040h 0064 4] PM1A Control Block Address : 00000604
+[044h 0068 4] PM1B Control Block Address : 00000000
+[048h 0072 4] PM2 Control Block Address : 00000000
+[04Ch 0076 4] PM Timer Block Address : 00000608
+[050h 0080 4] GPE0 Block Address : 00000620
+[054h 0084 4] GPE1 Block Address : 00000000
+[058h 0088 1] PM1 Event Block Length : 04
+[059h 0089 1] PM1 Control Block Length : 02
+[05Ah 0090 1] PM2 Control Block Length : 00
+[05Bh 0091 1] PM Timer Block Length : 04
+[05Ch 0092 1] GPE0 Block Length : 10
+[05Dh 0093 1] GPE1 Block Length : 00
+[05Eh 0094 1] GPE1 Base Offset : 00
+[05Fh 0095 1] _CST Support : 00
+[060h 0096 2] C2 Latency : 0FFF
+[062h 0098 2] C3 Latency : 0FFF
+[064h 0100 2] CPU Cache Size : 0000
+[066h 0102 2] Cache Flush Stride : 0000
+[068h 0104 1] Duty Cycle Offset : 00
+[069h 0105 1] Duty Cycle Width : 00
+[06Ah 0106 1] RTC Day Alarm Index : 00
+[06Bh 0107 1] RTC Month Alarm Index : 00
+[06Ch 0108 1] RTC Century Index : 32
+[06Dh 0109 2] Boot Flags (decoded below) : 0002
+ Legacy Devices Supported (V2) : 0
+ 8042 Present on ports 60/64 (V2) : 1
+ VGA Not Present (V4) : 0
+ MSI Not Supported (V4) : 0
+ PCIe ASPM Not Supported (V4) : 0
+ CMOS RTC Not Present (V5) : 0
+[06Fh 0111 1] Reserved : 00
+[070h 0112 4] Flags (decoded below) : 000484A5
+ WBINVD instruction is operational (V1) : 1
+ WBINVD flushes all caches (V1) : 0
+ All CPUs support C1 (V1) : 1
+ C2 works on MP system (V1) : 0
+ Control Method Power Button (V1) : 0
+ Control Method Sleep Button (V1) : 1
+ RTC wake not in fixed reg space (V1) : 0
+ RTC can wake system from S4 (V1) : 1
+ 32-bit PM Timer (V1) : 0
+ Docking Supported (V1) : 0
+ Reset Register Supported (V2) : 1
+ Sealed Case (V3) : 0
+ Headless - No Video (V3) : 0
+ Use native instr after SLP_TYPx (V3) : 0
+ PCIEXP_WAK Bits Supported (V4) : 0
+ Use Platform Timer (V4) : 1
+ RTC_STS valid on S4 wake (V4) : 0
+ Remote Power-on capable (V4) : 0
+ Use APIC Cluster Model (V4) : 1
+ Use APIC Physical Destination Mode (V4) : 0
+ Hardware Reduced (V5) : 0
+ Low Power S0 Idle (V5) : 0
+
+[074h 0116 12] Reset Register : [Generic Address Structure]
+[074h 0116 1] Space ID : 01 [SystemIO]
+[075h 0117 1] Bit Width : 08
+[076h 0118 1] Bit Offset : 00
+[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
+[078h 0120 8] Address : 0000000000000CF9
+
+[080h 0128 1] Value to cause reset : 0F
+[081h 0129 2] ARM Flags (decoded below) : 0000
+ PSCI Compliant : 0
+ Must use HVC for PSCI : 0
+
+[083h 0131 1] FADT Minor Revision : 00
+[084h 0132 8] FACS Address : 0000000000000000
+[08Ch 0140 8] DSDT Address : 0000000000000000
+[094h 0148 12] PM1A Event Block : [Generic Address Structure]
+[094h 0148 1] Space ID : 01 [SystemIO]
+[095h 0149 1] Bit Width : 20
+[096h 0150 1] Bit Offset : 00
+[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
+[098h 0152 8] Address : 0000000000000600
+
+[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
+[0A0h 0160 1] Space ID : 00 [SystemMemory]
+[0A1h 0161 1] Bit Width : 00
+[0A2h 0162 1] Bit Offset : 00
+[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0A4h 0164 8] Address : 0000000000000000
+
+[0ACh 0172 12] PM1A Control Block : [Generic Address Structure]
+[0ACh 0172 1] Space ID : 01 [SystemIO]
+[0ADh 0173 1] Bit Width : 10
+[0AEh 0174 1] Bit Offset : 00
+[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0B0h 0176 8] Address : 0000000000000604
+
+[0B8h 0184 12] PM1B Control Block : [Generic Address Structure]
+[0B8h 0184 1] Space ID : 00 [SystemMemory]
+[0B9h 0185 1] Bit Width : 00
+[0BAh 0186 1] Bit Offset : 00
+[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0BCh 0188 8] Address : 0000000000000000
+
+[0C4h 0196 12] PM2 Control Block : [Generic Address Structure]
+[0C4h 0196 1] Space ID : 00 [SystemMemory]
+[0C5h 0197 1] Bit Width : 00
+[0C6h 0198 1] Bit Offset : 00
+[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0C8h 0200 8] Address : 0000000000000000
+
+[0D0h 0208 12] PM Timer Block : [Generic Address Structure]
+[0D0h 0208 1] Space ID : 01 [SystemIO]
+[0D1h 0209 1] Bit Width : 20
+[0D2h 0210 1] Bit Offset : 00
+[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0D4h 0212 8] Address : 0000000000000608
+
+[0DCh 0220 12] GPE0 Block : [Generic Address Structure]
+[0DCh 0220 1] Space ID : 01 [SystemIO]
+[0DDh 0221 1] Bit Width : 80
+[0DEh 0222 1] Bit Offset : 00
+[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0E0h 0224 8] Address : 0000000000000620
+
+[0E8h 0232 12] GPE1 Block : [Generic Address Structure]
+[0E8h 0232 1] Space ID : 00 [SystemMemory]
+[0E9h 0233 1] Bit Width : 00
+[0EAh 0234 1] Bit Offset : 00
+[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0ECh 0236 8] Address : 0000000000000000
...
APIC:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly of /tmp/aml-WKE3C2, Mon Oct 23 15:25:01 2023
+ *
+ * ACPI Data Table [APIC]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)]
+[004h 0004 4] Table Length : 00000CA6
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : 2C
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Local Apic Address : FEE00000
+[028h 0040 4] Flags (decoded below) : 00000001
+ PC-AT Compatibility : 1
+
+[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
+[02Dh 0045 1] Length : 08
+[02Eh 0046 1] Processor ID : 00
+[02Fh 0047 1] Local Apic ID : 00
+[030h 0048 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[034h 0052 1] Subtable Type : 00 [Processor Local APIC]
+[035h 0053 1] Length : 08
+[036h 0054 1] Processor ID : 01
+[037h 0055 1] Local Apic ID : 01
+[038h 0056 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
[snip]
+[434h 1076 1] Subtable Type : 00 [Processor Local APIC]
+[435h 1077 1] Length : 08
+[436h 1078 1] Processor ID : 81
+[437h 1079 1] Local Apic ID : 81
+[438h 1080 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[43Ch 1084 1] Subtable Type : 09 [Processor Local x2APIC]
+[43Dh 1085 1] Length : 10
+[43Eh 1086 2] Reserved : 0000
+[440h 1088 4] Processor x2Apic ID : 00000100
+[444h 1092 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+[448h 1096 4] Processor UID : 00000082
[snip]
+[C4Ch 3148 1] Subtable Type : 09 [Processor Local x2APIC]
+[C4Dh 3149 1] Length : 10
+[C4Eh 3150 2] Reserved : 0000
+[C50h 3152 4] Processor x2Apic ID : 00000181
+[C54h 3156 4] Flags (decoded below) : 00000000
+ Processor Enabled : 0
+[C58h 3160 4] Processor UID : 00000103
+
+[C5Ch 3164 1] Subtable Type : 01 [I/O APIC]
+[C5Dh 3165 1] Length : 0C
+[C5Eh 3166 1] I/O Apic ID : 00
+[C5Fh 3167 1] Reserved : 00
+[C60h 3168 4] Address : FEC00000
+[C64h 3172 4] Interrupt : 00000000
+
+[C68h 3176 1] Subtable Type : 02 [Interrupt Source Override]
+[C69h 3177 1] Length : 0A
+[C6Ah 3178 1] Bus : 00
+[C6Bh 3179 1] Source : 00
+[C6Ch 3180 4] Interrupt : 00000002
+[C70h 3184 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
[snip]
+[C90h 3216 1] Subtable Type : 02 [Interrupt Source Override]
+[C91h 3217 1] Length : 0A
+[C92h 3218 1] Bus : 00
+[C93h 3219 1] Source : 0B
+[C94h 3220 4] Interrupt : 0000000B
+[C98h 3224 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[C9Ah 3226 1] Subtable Type : 0A [Local x2APIC NMI]
+[C9Bh 3227 1] Length : 0C
+[C9Ch 3228 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+[C9Eh 3230 4] Processor UID : FFFFFFFF
+[CA2h 3234 1] Interrupt Input LINT : 01
+[CA3h 3235 3] Reserved : 000000
...
DSDT:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembling to symbolic ASL+ operators
+ *
+ * Disassembly of /tmp/aml-CDE3C2, Mon Oct 23 15:25:01 2023
+ *
+ * Original Table Header:
+ * Signature "DSDT"
+ * Length 0x000083EA (33770)
+ * Revision 0x01 **** 32-bit table (V1), no 64-bit math support
+ * Checksum 0x01
+ * OEM ID "BOCHS "
+ * OEM Table ID "BXPC "
+ * OEM Revision 0x00000001 (1)
+ * Compiler ID "BXPC"
+ * Compiler Version 0x00000001 (1)
+ */
+DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)
+{
+ Scope (\)
+ {
+ OperationRegion (DBG, SystemIO, 0x0402, One)
+ Field (DBG, ByteAcc, NoLock, Preserve)
+ {
+ DBGB, 8
+ }
+
+ Method (DBUG, 1, NotSerialized)
+ {
+ ToHexString (Arg0, Local0)
+ ToBuffer (Local0, Local0)
+ Local1 = (SizeOf (Local0) - One)
+ Local2 = Zero
+ While ((Local2 < Local1))
+ {
+ DBGB = DerefOf (Local0 [Local2])
+ Local2++
+ }
+
+ DBGB = 0x0A
+ }
+ }
[snip]
+ Processor (C000, 0x00, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (Zero))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (Zero, Arg0, Arg1, Arg2)
+ }
+ }
[snip]
+ Processor (C081, 0x81, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (0x81))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x81, 0x81, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (0x81)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (0x81, Arg0, Arg1, Arg2)
+ }
+ }
...
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20231023094635.1588282-17-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
|
||
|
Zhao Liu
|
198eee0cc1 |
tests: bios-tables-test: Add test for smbios type4 thread count2
This tests the commit
|
||
|
Zhao Liu
|
7cb953ca19 |
tests: bios-tables-test: Prepare the ACPI table change for smbios type4 thread count2 test
Following the guidelines in tests/qtest/bios-tables-test.c, this is step 1 - 3. List the ACPI tables that will be added to test the thread count2 field of smbios type4 table. Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231023094635.1588282-15-zhao1.liu@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> |
||
|
Zhao Liu
|
a775cb191e |
tests: bios-tables-test: Add ACPI table binaries for smbios type4 thread count test
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 5 and 6.
Changes in the tables:
FACP:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly of /tmp/aml-1NP791, Wed Aug 23 21:51:31 2023
+ *
+ * ACPI Data Table [FACP]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)]
+[004h 0004 4] Table Length : 000000F4
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : B3
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] FACS Address : 00000000
+[028h 0040 4] DSDT Address : 00000000
+[02Ch 0044 1] Model : 01
+[02Dh 0045 1] PM Profile : 00 [Unspecified]
+[02Eh 0046 2] SCI Interrupt : 0009
+[030h 0048 4] SMI Command Port : 000000B2
+[034h 0052 1] ACPI Enable Value : 02
+[035h 0053 1] ACPI Disable Value : 03
+[036h 0054 1] S4BIOS Command : 00
+[037h 0055 1] P-State Control : 00
+[038h 0056 4] PM1A Event Block Address : 00000600
+[03Ch 0060 4] PM1B Event Block Address : 00000000
+[040h 0064 4] PM1A Control Block Address : 00000604
+[044h 0068 4] PM1B Control Block Address : 00000000
+[048h 0072 4] PM2 Control Block Address : 00000000
+[04Ch 0076 4] PM Timer Block Address : 00000608
+[050h 0080 4] GPE0 Block Address : 00000620
+[054h 0084 4] GPE1 Block Address : 00000000
+[058h 0088 1] PM1 Event Block Length : 04
+[059h 0089 1] PM1 Control Block Length : 02
+[05Ah 0090 1] PM2 Control Block Length : 00
+[05Bh 0091 1] PM Timer Block Length : 04
+[05Ch 0092 1] GPE0 Block Length : 10
+[05Dh 0093 1] GPE1 Block Length : 00
+[05Eh 0094 1] GPE1 Base Offset : 00
+[05Fh 0095 1] _CST Support : 00
+[060h 0096 2] C2 Latency : 0FFF
+[062h 0098 2] C3 Latency : 0FFF
+[064h 0100 2] CPU Cache Size : 0000
+[066h 0102 2] Cache Flush Stride : 0000
+[068h 0104 1] Duty Cycle Offset : 00
+[069h 0105 1] Duty Cycle Width : 00
+[06Ah 0106 1] RTC Day Alarm Index : 00
+[06Bh 0107 1] RTC Month Alarm Index : 00
+[06Ch 0108 1] RTC Century Index : 32
+[06Dh 0109 2] Boot Flags (decoded below) : 0002
+ Legacy Devices Supported (V2) : 0
+ 8042 Present on ports 60/64 (V2) : 1
+ VGA Not Present (V4) : 0
+ MSI Not Supported (V4) : 0
+ PCIe ASPM Not Supported (V4) : 0
+ CMOS RTC Not Present (V5) : 0
+[06Fh 0111 1] Reserved : 00
+[070h 0112 4] Flags (decoded below) : 000484A5
+ WBINVD instruction is operational (V1) : 1
+ WBINVD flushes all caches (V1) : 0
+ All CPUs support C1 (V1) : 1
+ C2 works on MP system (V1) : 0
+ Control Method Power Button (V1) : 0
+ Control Method Sleep Button (V1) : 1
+ RTC wake not in fixed reg space (V1) : 0
+ RTC can wake system from S4 (V1) : 1
+ 32-bit PM Timer (V1) : 0
+ Docking Supported (V1) : 0
+ Reset Register Supported (V2) : 1
+ Sealed Case (V3) : 0
+ Headless - No Video (V3) : 0
+ Use native instr after SLP_TYPx (V3) : 0
+ PCIEXP_WAK Bits Supported (V4) : 0
+ Use Platform Timer (V4) : 1
+ RTC_STS valid on S4 wake (V4) : 0
+ Remote Power-on capable (V4) : 0
+ Use APIC Cluster Model (V4) : 1
+ Use APIC Physical Destination Mode (V4) : 0
+ Hardware Reduced (V5) : 0
+ Low Power S0 Idle (V5) : 0
+
+[074h 0116 12] Reset Register : [Generic Address Structure]
+[074h 0116 1] Space ID : 01 [SystemIO]
+[075h 0117 1] Bit Width : 08
+[076h 0118 1] Bit Offset : 00
+[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
+[078h 0120 8] Address : 0000000000000CF9
+
+[080h 0128 1] Value to cause reset : 0F
+[081h 0129 2] ARM Flags (decoded below) : 0000
+ PSCI Compliant : 0
+ Must use HVC for PSCI : 0
+
+[083h 0131 1] FADT Minor Revision : 00
+[084h 0132 8] FACS Address : 0000000000000000
+[08Ch 0140 8] DSDT Address : 0000000000000000
+[094h 0148 12] PM1A Event Block : [Generic Address Structure]
+[094h 0148 1] Space ID : 01 [SystemIO]
+[095h 0149 1] Bit Width : 20
+[096h 0150 1] Bit Offset : 00
+[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
+[098h 0152 8] Address : 0000000000000600
+
+[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
+[0A0h 0160 1] Space ID : 00 [SystemMemory]
+[0A1h 0161 1] Bit Width : 00
+[0A2h 0162 1] Bit Offset : 00
+[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0A4h 0164 8] Address : 0000000000000000
+
+[0ACh 0172 12] PM1A Control Block : [Generic Address Structure]
+[0ACh 0172 1] Space ID : 01 [SystemIO]
+[0ADh 0173 1] Bit Width : 10
+[0AEh 0174 1] Bit Offset : 00
+[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0B0h 0176 8] Address : 0000000000000604
+
+[0B8h 0184 12] PM1B Control Block : [Generic Address Structure]
+[0B8h 0184 1] Space ID : 00 [SystemMemory]
+[0B9h 0185 1] Bit Width : 00
+[0BAh 0186 1] Bit Offset : 00
+[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0BCh 0188 8] Address : 0000000000000000
+
+[0C4h 0196 12] PM2 Control Block : [Generic Address Structure]
+[0C4h 0196 1] Space ID : 00 [SystemMemory]
+[0C5h 0197 1] Bit Width : 00
+[0C6h 0198 1] Bit Offset : 00
+[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0C8h 0200 8] Address : 0000000000000000
+
+[0D0h 0208 12] PM Timer Block : [Generic Address Structure]
+[0D0h 0208 1] Space ID : 01 [SystemIO]
+[0D1h 0209 1] Bit Width : 20
+[0D2h 0210 1] Bit Offset : 00
+[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0D4h 0212 8] Address : 0000000000000608
+
+[0DCh 0220 12] GPE0 Block : [Generic Address Structure]
+[0DCh 0220 1] Space ID : 01 [SystemIO]
+[0DDh 0221 1] Bit Width : 80
+[0DEh 0222 1] Bit Offset : 00
+[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0E0h 0224 8] Address : 0000000000000620
+
+[0E8h 0232 12] GPE1 Block : [Generic Address Structure]
+[0E8h 0232 1] Space ID : 00 [SystemMemory]
+[0E9h 0233 1] Bit Width : 00
+[0EAh 0234 1] Bit Offset : 00
+[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0ECh 0236 8] Address : 0000000000000000
...
APIC:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly of /tmp/aml-2JP791, Wed Aug 23 21:51:31 2023
+ *
+ * ACPI Data Table [APIC]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)]
+[004h 0004 4] Table Length : 00000220
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : 63
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Local Apic Address : FEE00000
+[028h 0040 4] Flags (decoded below) : 00000001
+ PC-AT Compatibility : 1
+
+[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
+[02Dh 0045 1] Length : 08
+[02Eh 0046 1] Processor ID : 00
+[02Fh 0047 1] Local Apic ID : 00
+[030h 0048 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[034h 0052 1] Subtable Type : 00 [Processor Local APIC]
+[035h 0053 1] Length : 08
+[036h 0054 1] Processor ID : 01
+[037h 0055 1] Local Apic ID : 01
+[038h 0056 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
[snip]
+[1D4h 0468 1] Subtable Type : 00 [Processor Local APIC]
+[1D5h 0469 1] Length : 08
+[1D6h 0470 1] Processor ID : 35
+[1D7h 0471 1] Local Apic ID : 6A
+[1D8h 0472 4] Flags (decoded below) : 00000000
+ Processor Enabled : 0
+ Runtime Online Capable : 0
+
+[1DCh 0476 1] Subtable Type : 01 [I/O APIC]
+[1DDh 0477 1] Length : 0C
+[1DEh 0478 1] I/O Apic ID : 00
+[1DFh 0479 1] Reserved : 00
+[1E0h 0480 4] Address : FEC00000
+[1E4h 0484 4] Interrupt : 00000000
+
+[1E8h 0488 1] Subtable Type : 02 [Interrupt Source Override]
+[1E9h 0489 1] Length : 0A
+[1EAh 0490 1] Bus : 00
+[1EBh 0491 1] Source : 00
+[1ECh 0492 4] Interrupt : 00000002
+[1F0h 0496 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+
+[1F2h 0498 1] Subtable Type : 02 [Interrupt Source Override]
+[1F3h 0499 1] Length : 0A
+[1F4h 0500 1] Bus : 00
+[1F5h 0501 1] Source : 05
+[1F6h 0502 4] Interrupt : 00000005
+[1FAh 0506 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[1FCh 0508 1] Subtable Type : 02 [Interrupt Source Override]
+[1FDh 0509 1] Length : 0A
+[1FEh 0510 1] Bus : 00
+[1FFh 0511 1] Source : 09
+[200h 0512 4] Interrupt : 00000009
+[204h 0516 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[206h 0518 1] Subtable Type : 02 [Interrupt Source Override]
+[207h 0519 1] Length : 0A
+[208h 0520 1] Bus : 00
+[209h 0521 1] Source : 0A
+[20Ah 0522 4] Interrupt : 0000000A
+[20Eh 0526 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[210h 0528 1] Subtable Type : 02 [Interrupt Source Override]
+[211h 0529 1] Length : 0A
+[212h 0530 1] Bus : 00
+[213h 0531 1] Source : 0B
+[214h 0532 4] Interrupt : 0000000B
+[218h 0536 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[21Ah 0538 1] Subtable Type : 04 [Local APIC NMI]
+[21Bh 0539 1] Length : 06
+[21Ch 0540 1] Processor ID : FF
+[21Dh 0541 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+[21Fh 0543 1] Interrupt Input LINT : 01
...
DSDT:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembling to symbolic ASL+ operators
+ *
+ * Disassembly of /tmp/aml-00O791, Wed Aug 23 21:51:31 2023
+ *
+ * Original Table Header:
+ * Signature "DSDT"
+ * Length 0x00003271 (12913)
+ * Revision 0x01 **** 32-bit table (V1), no 64-bit math support
+ * Checksum 0xAF
+ * OEM ID "BOCHS "
+ * OEM Table ID "BXPC "
+ * OEM Revision 0x00000001 (1)
+ * Compiler ID "BXPC"
+ * Compiler Version 0x00000001 (1)
+ */
+DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)
+{
+ Scope (\)
+ {
+ OperationRegion (DBG, SystemIO, 0x0402, One)
+ Field (DBG, ByteAcc, NoLock, Preserve)
+ {
+ DBGB, 8
+ }
+
+ Method (DBUG, 1, NotSerialized)
+ {
+ ToHexString (Arg0, Local0)
+ ToBuffer (Local0, Local0)
+ Local1 = (SizeOf (Local0) - One)
+ Local2 = Zero
+ While ((Local2 < Local1))
+ {
+ DBGB = DerefOf (Local0 [Local2])
+ Local2++
+ }
+
+ DBGB = 0x0A
+ }
+ }
[snip]
+ Processor (C000, 0x00, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (Zero))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (Zero, Arg0, Arg1, Arg2)
+ }
+ }
+
+ Processor (C001, 0x01, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (One))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (One)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (One, Arg0, Arg1, Arg2)
+ }
+ }
[snip]
+ Processor (C035, 0x35, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (0x35))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x35, 0x6A, 0x01, 0x00, 0x00, 0x00 // ..5j....
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (0x35)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (0x35, Arg0, Arg1, Arg2)
+ }
+ }
...
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231023094635.1588282-14-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
|
||
|
Zhao Liu
|
7ee18dcef1 |
tests: bios-tables-test: Add test for smbios type4 thread count
This tests the commit
|
||
|
Zhao Liu
|
85ccbe1275 |
tests: bios-tables-test: Prepare the ACPI table change for smbios type4 thread count test
Following the guidelines in tests/qtest/bios-tables-test.c, this is step 1 - 3. List the ACPI tables that will be added to test the thread count field of smbios type4 table. Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231023094635.1588282-12-zhao1.liu@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> |
||
|
Zhao Liu
|
f03359a85b |
tests: bios-tables-test: Update ACPI table binaries for smbios core count2 test
Change the core count2 from 275 to 260.
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 5 and 6.
Changes in the tables:
APIC:
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20200925 (64-bit version)
* Copyright (c) 2000 - 2020 Intel Corporation
*
- * Disassembly of tests/data/acpi/q35/APIC.core-count2, Wed Aug 23 16:29:51 2023
+ * Disassembly of /tmp/aml-KQDX91, Wed Aug 23 16:29:51 2023
*
* ACPI Data Table [APIC]
*
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
*/
[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)]
-[004h 0004 4] Table Length : 000009AE
+[004h 0004 4] Table Length : 00000CA6
[008h 0008 1] Revision : 03
-[009h 0009 1] Checksum : CE
+[009h 0009 1] Checksum : FA
[00Ah 0010 6] Oem ID : "BOCHS "
[010h 0016 8] Oem Table ID : "BXPC "
[018h 0024 4] Oem Revision : 00000001
[01Ch 0028 4] Asl Compiler ID : "BXPC"
[020h 0032 4] Asl Compiler Revision : 00000001
[024h 0036 4] Local Apic Address : FEE00000
[028h 0040 4] Flags (decoded below) : 00000001
PC-AT Compatibility : 1
[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
[02Dh 0045 1] Length : 08
[02Eh 0046 1] Processor ID : 00
[02Fh 0047 1] Local Apic ID : 00
[030h 0048 4] Flags (decoded below) : 00000001
Processor Enabled : 1
@@ -1051,1256 +1051,1136 @@
[42Ch 1068 1] Subtable Type : 00 [Processor Local APIC]
[42Dh 1069 1] Length : 08
[42Eh 1070 1] Processor ID : 80
[42Fh 1071 1] Local Apic ID : 80
[430h 1072 4] Flags (decoded below) : 00000001
Processor Enabled : 1
Runtime Online Capable : 0
[434h 1076 1] Subtable Type : 00 [Processor Local APIC]
[435h 1077 1] Length : 08
[436h 1078 1] Processor ID : 81
[437h 1079 1] Local Apic ID : 81
[438h 1080 4] Flags (decoded below) : 00000001
Processor Enabled : 1
Runtime Online Capable : 0
-[43Ch 1084 1] Subtable Type : 00 [Processor Local APIC]
-[43Dh 1085 1] Length : 08
-[43Eh 1086 1] Processor ID : 82
-[43Fh 1087 1] Local Apic ID : 82
-[440h 1088 4] Flags (decoded below) : 00000001
- Processor Enabled : 1
- Runtime Online Capable : 0
-
-[444h 1092 1] Subtable Type : 00 [Processor Local APIC]
-[445h 1093 1] Length : 08
-[446h 1094 1] Processor ID : 83
-[447h 1095 1] Local Apic ID : 83
-[448h 1096 4] Flags (decoded below) : 00000001
- Processor Enabled : 1
- Runtime Online Capable : 0
[snip]
-
-[964h 2404 1] Subtable Type : 01 [I/O APIC]
-[965h 2405 1] Length : 0C
-[966h 2406 1] I/O Apic ID : 00
-[967h 2407 1] Reserved : 00
-[968h 2408 4] Address : FEC00000
-[96Ch 2412 4] Interrupt : 00000000
-
-[970h 2416 1] Subtable Type : 02 [Interrupt Source Override]
-[971h 2417 1] Length : 0A
-[972h 2418 1] Bus : 00
-[973h 2419 1] Source : 00
-[974h 2420 4] Interrupt : 00000002
-[978h 2424 2] Flags (decoded below) : 0000
+[43Ch 1084 1] Subtable Type : 09 [Processor Local x2APIC]
+[43Dh 1085 1] Length : 10
+[43Eh 1086 2] Reserved : 0000
+[440h 1088 4] Processor x2Apic ID : 00000100
+[444h 1092 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+[448h 1096 4] Processor UID : 00000082
+
+[44Ch 1100 1] Subtable Type : 09 [Processor Local x2APIC]
+[44Dh 1101 1] Length : 10
+[44Eh 1102 2] Reserved : 0000
+[450h 1104 4] Processor x2Apic ID : 00000101
+[454h 1108 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+[458h 1112 4] Processor UID : 00000083
+
[snip]
+
+[C68h 3176 1] Subtable Type : 02 [Interrupt Source Override]
+[C69h 3177 1] Length : 0A
+[C6Ah 3178 1] Bus : 00
+[C6Bh 3179 1] Source : 00
+[C6Ch 3180 4] Interrupt : 00000002
+[C70h 3184 2] Flags (decoded below) : 0000
Polarity : 0
Trigger Mode : 0
-[97Ah 2426 1] Subtable Type : 02 [Interrupt Source Override]
-[97Bh 2427 1] Length : 0A
-[97Ch 2428 1] Bus : 00
-[97Dh 2429 1] Source : 05
-[97Eh 2430 4] Interrupt : 00000005
-[982h 2434 2] Flags (decoded below) : 000D
+[C72h 3186 1] Subtable Type : 02 [Interrupt Source Override]
+[C73h 3187 1] Length : 0A
+[C74h 3188 1] Bus : 00
+[C75h 3189 1] Source : 05
+[C76h 3190 4] Interrupt : 00000005
+[C7Ah 3194 2] Flags (decoded below) : 000D
Polarity : 1
Trigger Mode : 3
-[984h 2436 1] Subtable Type : 02 [Interrupt Source Override]
-[985h 2437 1] Length : 0A
-[986h 2438 1] Bus : 00
-[987h 2439 1] Source : 09
-[988h 2440 4] Interrupt : 00000009
-[98Ch 2444 2] Flags (decoded below) : 000D
+[C7Ch 3196 1] Subtable Type : 02 [Interrupt Source Override]
+[C7Dh 3197 1] Length : 0A
+[C7Eh 3198 1] Bus : 00
+[C7Fh 3199 1] Source : 09
+[C80h 3200 4] Interrupt : 00000009
+[C84h 3204 2] Flags (decoded below) : 000D
Polarity : 1
Trigger Mode : 3
-[98Eh 2446 1] Subtable Type : 02 [Interrupt Source Override]
-[98Fh 2447 1] Length : 0A
-[990h 2448 1] Bus : 00
-[991h 2449 1] Source : 0A
-[992h 2450 4] Interrupt : 0000000A
-[996h 2454 2] Flags (decoded below) : 000D
+[C86h 3206 1] Subtable Type : 02 [Interrupt Source Override]
+[C87h 3207 1] Length : 0A
+[C88h 3208 1] Bus : 00
+[C89h 3209 1] Source : 0A
+[C8Ah 3210 4] Interrupt : 0000000A
+[C8Eh 3214 2] Flags (decoded below) : 000D
Polarity : 1
Trigger Mode : 3
-[998h 2456 1] Subtable Type : 02 [Interrupt Source Override]
-[999h 2457 1] Length : 0A
-[99Ah 2458 1] Bus : 00
-[99Bh 2459 1] Source : 0B
-[99Ch 2460 4] Interrupt : 0000000B
-[9A0h 2464 2] Flags (decoded below) : 000D
+[C90h 3216 1] Subtable Type : 02 [Interrupt Source Override]
+[C91h 3217 1] Length : 0A
+[C92h 3218 1] Bus : 00
+[C93h 3219 1] Source : 0B
+[C94h 3220 4] Interrupt : 0000000B
+[C98h 3224 2] Flags (decoded below) : 000D
Polarity : 1
Trigger Mode : 3
-[9A2h 2466 1] Subtable Type : 0A [Local x2APIC NMI]
-[9A3h 2467 1] Length : 0C
-[9A4h 2468 2] Flags (decoded below) : 0000
+[C9Ah 3226 1] Subtable Type : 0A [Local x2APIC NMI]
+[C9Bh 3227 1] Length : 0C
+[C9Ch 3228 2] Flags (decoded below) : 0000
Polarity : 0
Trigger Mode : 0
-[9A6h 2470 4] Processor UID : FFFFFFFF
-[9AAh 2474 1] Interrupt Input LINT : 01
-[9ABh 2475 3] Reserved : 000000
+[C9Eh 3230 4] Processor UID : FFFFFFFF
+[CA2h 3234 1] Interrupt Input LINT : 01
+[CA3h 3235 3] Reserved : 000000
...
DSDT:
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20200925 (64-bit version)
* Copyright (c) 2000 - 2020 Intel Corporation
*
* Disassembling to symbolic ASL+ operators
*
- * Disassembly of tests/data/acpi/q35/DSDT.core-count2, Wed Aug 23 16:29:51 2023
+ * Disassembly of /tmp/aml-6DDX91, Wed Aug 23 16:29:51 2023
*
* Original Table Header:
* Signature "DSDT"
- * Length 0x00007EEF (32495)
+ * Length 0x000083EA (33770)
* Revision 0x01 **** 32-bit table (V1), no 64-bit math support
- * Checksum 0x52
+ * Checksum 0x01
* OEM ID "BOCHS "
* OEM Table ID "BXPC "
* OEM Revision 0x00000001 (1)
* Compiler ID "BXPC"
* Compiler Version 0x00000001 (1)
*/
DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)
{
Scope (\)
{
OperationRegion (DBG, SystemIO, 0x0402, One)
Field (DBG, ByteAcc, NoLock, Preserve)
{
DBGB, 8
}
@@ -4196,107 +4196,32 @@
}
If ((Arg0 == 0x0101))
{
Notify (C101, Arg1)
}
If ((Arg0 == 0x0102))
{
Notify (C102, Arg1)
}
If ((Arg0 == 0x0103))
{
Notify (C103, Arg1)
}
-
- If ((Arg0 == 0x0104))
- {
- Notify (C104, Arg1)
- }
-
- If ((Arg0 == 0x0105))
- {
- Notify (C105, Arg1)
- }
-
- If ((Arg0 == 0x0106))
- {
- Notify (C106, Arg1)
- }
-
[snip]
- If ((Arg0 == 0x0112))
- {
- Notify (C112, Arg1)
- }
}
Method (CSTA, 1, Serialized)
{
Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
\_SB.PCI0.PRES.CSEL = Arg0
Local0 = Zero
If ((\_SB.PCI0.PRES.CPEN == One))
{
Local0 = 0x0F
}
Release (\_SB.PCI0.PRES.CPLK)
Return (Local0)
}
@@ -4306,33 +4231,33 @@
\_SB.PCI0.PRES.CSEL = Arg0
\_SB.PCI0.PRES.CEJ0 = One
Release (\_SB.PCI0.PRES.CPLK)
}
Method (CSCN, 0, Serialized)
{
Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
Name (CNEW, Package (0xFF) {})
Local3 = Zero
Local4 = One
While ((Local4 == One))
{
Local4 = Zero
Local0 = One
Local1 = Zero
- While (((Local0 == One) && (Local3 < 0x0113)))
+ While (((Local0 == One) && (Local3 < 0x0104)))
{
Local0 = Zero
\_SB.PCI0.PRES.CSEL = Local3
\_SB.PCI0.PRES.CCMD = Zero
If ((\_SB.PCI0.PRES.CDAT < Local3))
{
Break
}
If ((Local1 == 0xFF))
{
Local4 = One
Break
}
Local3 = \_SB.PCI0.PRES.CDAT
@@ -7220,3281 +7145,3281 @@
Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
{
0x00, 0x08, 0x81, 0x81, 0x01, 0x00, 0x00, 0x00 // ........
})
Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
{
CEJ0 (0x81)
}
Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
{
COST (0x81, Arg0, Arg1, Arg2)
}
}
- Processor (C082, 0x82, 0x00000000, 0x00)
+ Device (C082)
{
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x82) // _UID: Unique ID
Method (_STA, 0, Serialized) // _STA: Status
{
Return (CSTA (0x82))
}
- Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ Name (_MAT, Buffer (0x10) // _MAT: Multiple APIC Table Entry
{
- 0x00, 0x08, 0x82, 0x82, 0x01, 0x00, 0x00, 0x00 // ........
+ /* 0000 */ 0x09, 0x10, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, // ........
+ /* 0008 */ 0x01, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00, 0x00 // ........
})
Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
{
CEJ0 (0x82)
}
Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
{
COST (0x82, Arg0, Arg1, Arg2)
}
}
- Processor (C083, 0x83, 0x00000000, 0x00)
+ Device (C083)
{
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x83) // _UID: Unique ID
Method (_STA, 0, Serialized) // _STA: Status
{
Return (CSTA (0x83))
}
- Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ Name (_MAT, Buffer (0x10) // _MAT: Multiple APIC Table Entry
{
- 0x00, 0x08, 0x83, 0x83, 0x01, 0x00, 0x00, 0x00 // ........
+ /* 0000 */ 0x09, 0x10, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, // ........
+ /* 0008 */ 0x01, 0x00, 0x00, 0x00, 0x83, 0x00, 0x00, 0x00 // ........
})
Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
{
CEJ0 (0x83)
}
Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
{
COST (0x83, Arg0, Arg1, Arg2)
}
}
- Processor (C084, 0x84, 0x00000000, 0x00)
+ Device (C084)
{
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x84) // _UID: Unique ID
Method (_STA, 0, Serialized) // _STA: Status
{
Return (CSTA (0x84))
}
- Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ Name (_MAT, Buffer (0x10) // _MAT: Multiple APIC Table Entry
{
- 0x00, 0x08, 0x84, 0x84, 0x01, 0x00, 0x00, 0x00 // ........
+ /* 0000 */ 0x09, 0x10, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, // ........
+ /* 0008 */ 0x01, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0x00 // ........
})
Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
{
CEJ0 (0x84)
}
Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
{
COST (0x84, Arg0, Arg1, Arg2)
}
}
[snip]
- Processor (C0FE, 0xFE, 0x00000000, 0x00)
+ Device (C0FE)
{
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0xFE) // _UID: Unique ID
Method (_STA, 0, Serialized) // _STA: Status
{
Return (CSTA (0xFE))
}
- Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ Name (_MAT, Buffer (0x10) // _MAT: Multiple APIC Table Entry
{
- 0x00, 0x08, 0xFE, 0xFE, 0x01, 0x00, 0x00, 0x00 // ........
+ /* 0000 */ 0x09, 0x10, 0x00, 0x00, 0x7C, 0x01, 0x00, 0x00, // ....|...
+ /* 0008 */ 0x01, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x00 // ........
})
Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
{
CEJ0 (0xFE)
}
Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
{
COST (0xFE, Arg0, Arg1, Arg2)
}
}
...
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231023094635.1588282-11-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
|
||
|
Zhao Liu
|
6dc82e3222 |
tests: bios-tables-test: Extend smbios core count2 test to cover general topology
The commit
|
||
|
Zhao Liu
|
c63fcb2c10 |
tests: bios-tables-test: Prepare the ACPI table change for smbios type4 core count2 test
Following the guidelines in tests/qtest/bios-tables-test.c, this is step 1 - 3. List the ACPI tables that will be changed about the type 4 core count2 test case. Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231023094635.1588282-9-zhao1.liu@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> |
||
|
Zhao Liu
|
61ace1d772 |
tests: bios-tables-test: Add ACPI table binaries for smbios type4 core count test
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 5 and 6.
Changes in the tables:
FACP:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly of /tmp/aml-Y6WW91, Wed Aug 23 15:43:43 2023
+ *
+ * ACPI Data Table [FACP]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)]
+[004h 0004 4] Table Length : 000000F4
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : B3
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] FACS Address : 00000000
+[028h 0040 4] DSDT Address : 00000000
+[02Ch 0044 1] Model : 01
+[02Dh 0045 1] PM Profile : 00 [Unspecified]
+[02Eh 0046 2] SCI Interrupt : 0009
+[030h 0048 4] SMI Command Port : 000000B2
+[034h 0052 1] ACPI Enable Value : 02
+[035h 0053 1] ACPI Disable Value : 03
+[036h 0054 1] S4BIOS Command : 00
+[037h 0055 1] P-State Control : 00
+[038h 0056 4] PM1A Event Block Address : 00000600
+[03Ch 0060 4] PM1B Event Block Address : 00000000
+[040h 0064 4] PM1A Control Block Address : 00000604
+[044h 0068 4] PM1B Control Block Address : 00000000
+[048h 0072 4] PM2 Control Block Address : 00000000
+[04Ch 0076 4] PM Timer Block Address : 00000608
+[050h 0080 4] GPE0 Block Address : 00000620
+[054h 0084 4] GPE1 Block Address : 00000000
+[058h 0088 1] PM1 Event Block Length : 04
+[059h 0089 1] PM1 Control Block Length : 02
+[05Ah 0090 1] PM2 Control Block Length : 00
+[05Bh 0091 1] PM Timer Block Length : 04
+[05Ch 0092 1] GPE0 Block Length : 10
+[05Dh 0093 1] GPE1 Block Length : 00
+[05Eh 0094 1] GPE1 Base Offset : 00
+[05Fh 0095 1] _CST Support : 00
+[060h 0096 2] C2 Latency : 0FFF
+[062h 0098 2] C3 Latency : 0FFF
+[064h 0100 2] CPU Cache Size : 0000
+[066h 0102 2] Cache Flush Stride : 0000
+[068h 0104 1] Duty Cycle Offset : 00
+[069h 0105 1] Duty Cycle Width : 00
+[06Ah 0106 1] RTC Day Alarm Index : 00
+[06Bh 0107 1] RTC Month Alarm Index : 00
+[06Ch 0108 1] RTC Century Index : 32
+[06Dh 0109 2] Boot Flags (decoded below) : 0002
+ Legacy Devices Supported (V2) : 0
+ 8042 Present on ports 60/64 (V2) : 1
+ VGA Not Present (V4) : 0
+ MSI Not Supported (V4) : 0
+ PCIe ASPM Not Supported (V4) : 0
+ CMOS RTC Not Present (V5) : 0
+[06Fh 0111 1] Reserved : 00
+[070h 0112 4] Flags (decoded below) : 000484A5
+ WBINVD instruction is operational (V1) : 1
+ WBINVD flushes all caches (V1) : 0
+ All CPUs support C1 (V1) : 1
+ C2 works on MP system (V1) : 0
+ Control Method Power Button (V1) : 0
+ Control Method Sleep Button (V1) : 1
+ RTC wake not in fixed reg space (V1) : 0
+ RTC can wake system from S4 (V1) : 1
+ 32-bit PM Timer (V1) : 0
+ Docking Supported (V1) : 0
+ Reset Register Supported (V2) : 1
+ Sealed Case (V3) : 0
+ Headless - No Video (V3) : 0
+ Use native instr after SLP_TYPx (V3) : 0
+ PCIEXP_WAK Bits Supported (V4) : 0
+ Use Platform Timer (V4) : 1
+ RTC_STS valid on S4 wake (V4) : 0
+ Remote Power-on capable (V4) : 0
+ Use APIC Cluster Model (V4) : 1
+ Use APIC Physical Destination Mode (V4) : 0
+ Hardware Reduced (V5) : 0
+ Low Power S0 Idle (V5) : 0
+
+[074h 0116 12] Reset Register : [Generic Address Structure]
+[074h 0116 1] Space ID : 01 [SystemIO]
+[075h 0117 1] Bit Width : 08
+[076h 0118 1] Bit Offset : 00
+[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
+[078h 0120 8] Address : 0000000000000CF9
+
+[080h 0128 1] Value to cause reset : 0F
+[081h 0129 2] ARM Flags (decoded below) : 0000
+ PSCI Compliant : 0
+ Must use HVC for PSCI : 0
+
+[083h 0131 1] FADT Minor Revision : 00
+[084h 0132 8] FACS Address : 0000000000000000
+[08Ch 0140 8] DSDT Address : 0000000000000000
+[094h 0148 12] PM1A Event Block : [Generic Address Structure]
+[094h 0148 1] Space ID : 01 [SystemIO]
+[095h 0149 1] Bit Width : 20
+[096h 0150 1] Bit Offset : 00
+[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
+[098h 0152 8] Address : 0000000000000600
+
+[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
+[0A0h 0160 1] Space ID : 00 [SystemMemory]
+[0A1h 0161 1] Bit Width : 00
+[0A2h 0162 1] Bit Offset : 00
+[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0A4h 0164 8] Address : 0000000000000000
+
+[0ACh 0172 12] PM1A Control Block : [Generic Address Structure]
+[0ACh 0172 1] Space ID : 01 [SystemIO]
+[0ADh 0173 1] Bit Width : 10
+[0AEh 0174 1] Bit Offset : 00
+[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0B0h 0176 8] Address : 0000000000000604
+
+[0B8h 0184 12] PM1B Control Block : [Generic Address Structure]
+[0B8h 0184 1] Space ID : 00 [SystemMemory]
+[0B9h 0185 1] Bit Width : 00
+[0BAh 0186 1] Bit Offset : 00
+[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0BCh 0188 8] Address : 0000000000000000
+
+[0C4h 0196 12] PM2 Control Block : [Generic Address Structure]
+[0C4h 0196 1] Space ID : 00 [SystemMemory]
+[0C5h 0197 1] Bit Width : 00
+[0C6h 0198 1] Bit Offset : 00
+[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0C8h 0200 8] Address : 0000000000000000
+
+[0D0h 0208 12] PM Timer Block : [Generic Address Structure]
+[0D0h 0208 1] Space ID : 01 [SystemIO]
+[0D1h 0209 1] Bit Width : 20
+[0D2h 0210 1] Bit Offset : 00
+[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0D4h 0212 8] Address : 0000000000000608
+
+[0DCh 0220 12] GPE0 Block : [Generic Address Structure]
+[0DCh 0220 1] Space ID : 01 [SystemIO]
+[0DDh 0221 1] Bit Width : 80
+[0DEh 0222 1] Bit Offset : 00
+[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0E0h 0224 8] Address : 0000000000000620
+
+[0E8h 0232 12] GPE1 Block : [Generic Address Structure]
+[0E8h 0232 1] Space ID : 00 [SystemMemory]
+[0E9h 0233 1] Bit Width : 00
+[0EAh 0234 1] Bit Offset : 00
+[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0ECh 0236 8] Address : 0000000000000000
...
APIC:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly of /tmp/aml-FFXW91, Wed Aug 23 15:43:43 2023
+ *
+ * ACPI Data Table [APIC]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)]
+[004h 0004 4] Table Length : 00000220
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : 3C
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Local Apic Address : FEE00000
+[028h 0040 4] Flags (decoded below) : 00000001
+ PC-AT Compatibility : 1
+
+[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
+[02Dh 0045 1] Length : 08
+[02Eh 0046 1] Processor ID : 00
+[02Fh 0047 1] Local Apic ID : 00
+[030h 0048 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
[snip]
+[1D4h 0468 1] Subtable Type : 00 [Processor Local APIC]
+[1D5h 0469 1] Length : 08
+[1D6h 0470 1] Processor ID : 35
+[1D7h 0471 1] Local Apic ID : 6A
+[1D8h 0472 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[1DCh 0476 1] Subtable Type : 01 [I/O APIC]
+[1DDh 0477 1] Length : 0C
+[1DEh 0478 1] I/O Apic ID : 00
+[1DFh 0479 1] Reserved : 00
+[1E0h 0480 4] Address : FEC00000
+[1E4h 0484 4] Interrupt : 00000000
+
+[1E8h 0488 1] Subtable Type : 02 [Interrupt Source Override]
+[1E9h 0489 1] Length : 0A
+[1EAh 0490 1] Bus : 00
+[1EBh 0491 1] Source : 00
+[1ECh 0492 4] Interrupt : 00000002
+[1F0h 0496 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+
+[1F2h 0498 1] Subtable Type : 02 [Interrupt Source Override]
+[1F3h 0499 1] Length : 0A
+[1F4h 0500 1] Bus : 00
+[1F5h 0501 1] Source : 05
+[1F6h 0502 4] Interrupt : 00000005
+[1FAh 0506 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[1FCh 0508 1] Subtable Type : 02 [Interrupt Source Override]
+[1FDh 0509 1] Length : 0A
+[1FEh 0510 1] Bus : 00
+[1FFh 0511 1] Source : 09
+[200h 0512 4] Interrupt : 00000009
+[204h 0516 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[206h 0518 1] Subtable Type : 02 [Interrupt Source Override]
+[207h 0519 1] Length : 0A
+[208h 0520 1] Bus : 00
+[209h 0521 1] Source : 0A
+[20Ah 0522 4] Interrupt : 0000000A
+[20Eh 0526 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[210h 0528 1] Subtable Type : 02 [Interrupt Source Override]
+[211h 0529 1] Length : 0A
+[212h 0530 1] Bus : 00
+[213h 0531 1] Source : 0B
+[214h 0532 4] Interrupt : 0000000B
+[218h 0536 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[21Ah 0538 1] Subtable Type : 04 [Local APIC NMI]
+[21Bh 0539 1] Length : 06
+[21Ch 0540 1] Processor ID : FF
+[21Dh 0541 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+[21Fh 0543 1] Interrupt Input LINT : 01
...
DSDT:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembling to symbolic ASL+ operators
+ *
+ * Disassembly of /tmp/aml-9ZXW91, Wed Aug 23 15:43:43 2023
+ *
+ * Original Table Header:
+ * Signature "DSDT"
+ * Length 0x00003271 (12913)
+ * Revision 0x01 **** 32-bit table (V1), no 64-bit math support
+ * Checksum 0xAF
+ * OEM ID "BOCHS "
+ * OEM Table ID "BXPC "
+ * OEM Revision 0x00000001 (1)
+ * Compiler ID "BXPC"
+ * Compiler Version 0x00000001 (1)
+ */
+DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)
+{
+ Scope (\)
+ {
+ OperationRegion (DBG, SystemIO, 0x0402, One)
+ Field (DBG, ByteAcc, NoLock, Preserve)
+ {
+ DBGB, 8
+ }
+
+ Method (DBUG, 1, NotSerialized)
+ {
+ ToHexString (Arg0, Local0)
+ ToBuffer (Local0, Local0)
+ Local1 = (SizeOf (Local0) - One)
+ Local2 = Zero
+ While ((Local2 < Local1))
+ {
+ DBGB = DerefOf (Local0 [Local2])
+ Local2++
+ }
+
+ DBGB = 0x0A
+ }
+ }
[snip]
+ Device (\_SB.CPUS)
+ {
+ Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
+ Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID
+ Method (CTFY, 2, NotSerialized)
+ {
+ If ((Arg0 == Zero))
+ {
+ Notify (C000, Arg1)
+ }
+
+ If ((Arg0 == One))
+ {
+ Notify (C001, Arg1)
+ }
[snip]
+ If ((Arg0 == 0x35))
+ {
+ Notify (C035, Arg1)
+ }
+ }
[snip]
+ Processor (C000, 0x00, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (Zero))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (Zero, Arg0, Arg1, Arg2)
+ }
+ }
+
+ Processor (C001, 0x01, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (One))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (One)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (One, Arg0, Arg1, Arg2)
+ }
+ }
[snip]
+ Processor (C035, 0x35, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (0x35))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x35, 0x6A, 0x01, 0x00, 0x00, 0x00 // ..5j....
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (0x35)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (0x35, Arg0, Arg1, Arg2)
+ }
+ }
...
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231023094635.1588282-8-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
|
||
|
Zhao Liu
|
148a8a1d5f |
tests: bios-tables-test: Add test for smbios type4 core count
This tests the commit
|
||
|
Zhao Liu
|
623d26ad9a |
tests: bios-tables-test: Prepare the ACPI table change for smbios type4 core count test
Following the guidelines in tests/qtest/bios-tables-test.c, this is step 1 - 3. List the ACPI tables that will be added to test the type 4 core count field. Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231023094635.1588282-6-zhao1.liu@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> |
||
|
Zhao Liu
|
c1cd1d360d |
tests: bios-tables-test: Add ACPI table binaries for smbios type4 count test
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 5 and 6.
Changes in the tables:
FACP:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly of /tmp/aml-W37791, Wed Aug 23 10:36:32 2023
+ *
+ * ACPI Data Table [FACP]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)]
+[004h 0004 4] Table Length : 000000F4
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : B3
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] FACS Address : 00000000
+[028h 0040 4] DSDT Address : 00000000
+[02Ch 0044 1] Model : 01
+[02Dh 0045 1] PM Profile : 00 [Unspecified]
+[02Eh 0046 2] SCI Interrupt : 0009
+[030h 0048 4] SMI Command Port : 000000B2
+[034h 0052 1] ACPI Enable Value : 02
+[035h 0053 1] ACPI Disable Value : 03
+[036h 0054 1] S4BIOS Command : 00
+[037h 0055 1] P-State Control : 00
+[038h 0056 4] PM1A Event Block Address : 00000600
+[03Ch 0060 4] PM1B Event Block Address : 00000000
+[040h 0064 4] PM1A Control Block Address : 00000604
+[044h 0068 4] PM1B Control Block Address : 00000000
+[048h 0072 4] PM2 Control Block Address : 00000000
+[04Ch 0076 4] PM Timer Block Address : 00000608
+[050h 0080 4] GPE0 Block Address : 00000620
+[054h 0084 4] GPE1 Block Address : 00000000
+[058h 0088 1] PM1 Event Block Length : 04
+[059h 0089 1] PM1 Control Block Length : 02
+[05Ah 0090 1] PM2 Control Block Length : 00
+[05Bh 0091 1] PM Timer Block Length : 04
+[05Ch 0092 1] GPE0 Block Length : 10
+[05Dh 0093 1] GPE1 Block Length : 00
+[05Eh 0094 1] GPE1 Base Offset : 00
+[05Fh 0095 1] _CST Support : 00
+[060h 0096 2] C2 Latency : 0FFF
+[062h 0098 2] C3 Latency : 0FFF
+[064h 0100 2] CPU Cache Size : 0000
+[066h 0102 2] Cache Flush Stride : 0000
+[068h 0104 1] Duty Cycle Offset : 00
+[069h 0105 1] Duty Cycle Width : 00
+[06Ah 0106 1] RTC Day Alarm Index : 00
+[06Bh 0107 1] RTC Month Alarm Index : 00
+[06Ch 0108 1] RTC Century Index : 32
+[06Dh 0109 2] Boot Flags (decoded below) : 0002
+ Legacy Devices Supported (V2) : 0
+ 8042 Present on ports 60/64 (V2) : 1
+ VGA Not Present (V4) : 0
+ MSI Not Supported (V4) : 0
+ PCIe ASPM Not Supported (V4) : 0
+ CMOS RTC Not Present (V5) : 0
+[06Fh 0111 1] Reserved : 00
+[070h 0112 4] Flags (decoded below) : 000484A5
+ WBINVD instruction is operational (V1) : 1
+ WBINVD flushes all caches (V1) : 0
+ All CPUs support C1 (V1) : 1
+ C2 works on MP system (V1) : 0
+ Control Method Power Button (V1) : 0
+ Control Method Sleep Button (V1) : 1
+ RTC wake not in fixed reg space (V1) : 0
+ RTC can wake system from S4 (V1) : 1
+ 32-bit PM Timer (V1) : 0
+ Docking Supported (V1) : 0
+ Reset Register Supported (V2) : 1
+ Sealed Case (V3) : 0
+ Headless - No Video (V3) : 0
+ Use native instr after SLP_TYPx (V3) : 0
+ PCIEXP_WAK Bits Supported (V4) : 0
+ Use Platform Timer (V4) : 1
+ RTC_STS valid on S4 wake (V4) : 0
+ Remote Power-on capable (V4) : 0
+ Use APIC Cluster Model (V4) : 1
+ Use APIC Physical Destination Mode (V4) : 0
+ Hardware Reduced (V5) : 0
+ Low Power S0 Idle (V5) : 0
+
+[074h 0116 12] Reset Register : [Generic Address Structure]
+[074h 0116 1] Space ID : 01 [SystemIO]
+[075h 0117 1] Bit Width : 08
+[076h 0118 1] Bit Offset : 00
+[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
+[078h 0120 8] Address : 0000000000000CF9
+
+[080h 0128 1] Value to cause reset : 0F
+[081h 0129 2] ARM Flags (decoded below) : 0000
+ PSCI Compliant : 0
+ Must use HVC for PSCI : 0
+
+[083h 0131 1] FADT Minor Revision : 00
+[084h 0132 8] FACS Address : 0000000000000000
+[08Ch 0140 8] DSDT Address : 0000000000000000
+[094h 0148 12] PM1A Event Block : [Generic Address Structure]
+[094h 0148 1] Space ID : 01 [SystemIO]
+[095h 0149 1] Bit Width : 20
+[096h 0150 1] Bit Offset : 00
+[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
+[098h 0152 8] Address : 0000000000000600
+
+[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
+[0A0h 0160 1] Space ID : 00 [SystemMemory]
+[0A1h 0161 1] Bit Width : 00
+[0A2h 0162 1] Bit Offset : 00
+[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0A4h 0164 8] Address : 0000000000000000
+
+[0ACh 0172 12] PM1A Control Block : [Generic Address Structure]
+[0ACh 0172 1] Space ID : 01 [SystemIO]
+[0ADh 0173 1] Bit Width : 10
+[0AEh 0174 1] Bit Offset : 00
+[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0B0h 0176 8] Address : 0000000000000604
+
+[0B8h 0184 12] PM1B Control Block : [Generic Address Structure]
+[0B8h 0184 1] Space ID : 00 [SystemMemory]
+[0B9h 0185 1] Bit Width : 00
+[0BAh 0186 1] Bit Offset : 00
+[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0BCh 0188 8] Address : 0000000000000000
+
+[0C4h 0196 12] PM2 Control Block : [Generic Address Structure]
+[0C4h 0196 1] Space ID : 00 [SystemMemory]
+[0C5h 0197 1] Bit Width : 00
+[0C6h 0198 1] Bit Offset : 00
+[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0C8h 0200 8] Address : 0000000000000000
+
+[0D0h 0208 12] PM Timer Block : [Generic Address Structure]
+[0D0h 0208 1] Space ID : 01 [SystemIO]
+[0D1h 0209 1] Bit Width : 20
+[0D2h 0210 1] Bit Offset : 00
+[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0D4h 0212 8] Address : 0000000000000608
+
+[0DCh 0220 12] GPE0 Block : [Generic Address Structure]
+[0DCh 0220 1] Space ID : 01 [SystemIO]
+[0DDh 0221 1] Bit Width : 80
+[0DEh 0222 1] Bit Offset : 00
+[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0E0h 0224 8] Address : 0000000000000620
+
+[0E8h 0232 12] GPE1 Block : [Generic Address Structure]
+[0E8h 0232 1] Space ID : 00 [SystemMemory]
+[0E9h 0233 1] Bit Width : 00
+[0EAh 0234 1] Bit Offset : 00
+[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0ECh 0236 8] Address : 0000000000000000
+
...
APIC:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly of /tmp/aml-687791, Wed Aug 23 10:36:32 2023
+ *
+ * ACPI Data Table [APIC]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)]
+[004h 0004 4] Table Length : 00000430
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : C5
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Local Apic Address : FEE00000
+[028h 0040 4] Flags (decoded below) : 00000001
+ PC-AT Compatibility : 1
+
+[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
+[02Dh 0045 1] Length : 08
+[02Eh 0046 1] Processor ID : 00
+[02Fh 0047 1] Local Apic ID : 00
+[030h 0048 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[034h 0052 1] Subtable Type : 00 [Processor Local APIC]
+[035h 0053 1] Length : 08
+[036h 0054 1] Processor ID : 01
+[037h 0055 1] Local Apic ID : 01
+[038h 0056 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
[snip]
+[3E4h 0996 1] Subtable Type : 00 [Processor Local APIC]
+[3E5h 0997 1] Length : 08
+[3E6h 0998 1] Processor ID : 77
+[3E7h 0999 1] Local Apic ID : 9E
+[3E8h 1000 4] Flags (decoded below) : 00000000
+ Processor Enabled : 0
+ Runtime Online Capable : 0
+
+[3ECh 1004 1] Subtable Type : 01 [I/O APIC]
+[3EDh 1005 1] Length : 0C
+[3EEh 1006 1] I/O Apic ID : 00
+[3EFh 1007 1] Reserved : 00
+[3F0h 1008 4] Address : FEC00000
+[3F4h 1012 4] Interrupt : 00000000
+
+[3F8h 1016 1] Subtable Type : 02 [Interrupt Source Override]
+[3F9h 1017 1] Length : 0A
+[3FAh 1018 1] Bus : 00
+[3FBh 1019 1] Source : 00
+[3FCh 1020 4] Interrupt : 00000002
+[400h 1024 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+
+[402h 1026 1] Subtable Type : 02 [Interrupt Source Override]
+[403h 1027 1] Length : 0A
+[404h 1028 1] Bus : 00
+[405h 1029 1] Source : 05
+[406h 1030 4] Interrupt : 00000005
+[40Ah 1034 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[40Ch 1036 1] Subtable Type : 02 [Interrupt Source Override]
+[40Dh 1037 1] Length : 0A
+[40Eh 1038 1] Bus : 00
+[40Fh 1039 1] Source : 09
+[410h 1040 4] Interrupt : 00000009
+[414h 1044 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[416h 1046 1] Subtable Type : 02 [Interrupt Source Override]
+[417h 1047 1] Length : 0A
+[418h 1048 1] Bus : 00
+[419h 1049 1] Source : 0A
+[41Ah 1050 4] Interrupt : 0000000A
+[41Eh 1054 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[420h 1056 1] Subtable Type : 02 [Interrupt Source Override]
+[421h 1057 1] Length : 0A
+[422h 1058 1] Bus : 00
+[423h 1059 1] Source : 0B
+[424h 1060 4] Interrupt : 0000000B
+[428h 1064 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[42Ah 1066 1] Subtable Type : 04 [Local APIC NMI]
+[42Bh 1067 1] Length : 06
+[42Ch 1068 1] Processor ID : FF
+[42Dh 1069 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+[42Fh 1071 1] Interrupt Input LINT : 01
+
...
DSDT:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembling to symbolic ASL+ operators
+ *
+ * Disassembly of /tmp/aml-8G8791, Wed Aug 23 10:36:32 2023
+ *
+ * Original Table Header:
+ * Signature "DSDT"
+ * Length 0x0000489D (18589)
+ * Revision 0x01 **** 32-bit table (V1), no 64-bit math support
+ * Checksum 0xDB
+ * OEM ID "BOCHS "
+ * OEM Table ID "BXPC "
+ * OEM Revision 0x00000001 (1)
+ * Compiler ID "BXPC"
+ * Compiler Version 0x00000001 (1)
+ */
+DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)
+{
+ Scope (\)
+ {
+ OperationRegion (DBG, SystemIO, 0x0402, One)
+ Field (DBG, ByteAcc, NoLock, Preserve)
+ {
+ DBGB, 8
+ }
+
+ Method (DBUG, 1, NotSerialized)
+ {
+ ToHexString (Arg0, Local0)
+ ToBuffer (Local0, Local0)
+ Local1 = (SizeOf (Local0) - One)
+ Local2 = Zero
+ While ((Local2 < Local1))
+ {
+ DBGB = DerefOf (Local0 [Local2])
+ Local2++
+ }
+
+ DBGB = 0x0A
+ }
+ }
+
[snip]
+
+ Processor (C000, 0x00, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (Zero))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (Zero, Arg0, Arg1, Arg2)
+ }
+ }
+
+ Processor (C001, 0x01, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (One))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (One)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (One, Arg0, Arg1, Arg2)
+ }
+ }
[snip]
+ Processor (C077, 0x77, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (0x77))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x77, 0x9E, 0x01, 0x00, 0x00, 0x00 // ..w.....
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (0x77)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (0x77, Arg0, Arg1, Arg2)
+ }
+ }
+ }
+ }
+
...
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231023094635.1588282-5-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
|
||
|
Zhao Liu
|
df210963a1 |
tests: bios-tables-test: Add test for smbios type4 count
This tests the commit
|
||
|
Zhao Liu
|
6c7937ece9 |
tests: bios-tables-test: Prepare the ACPI table change for smbios type4 count test
Following the guidelines in tests/qtest/bios-tables-test.c, this is step 1 - 3. List the ACPI tables that will be added to test the type 4 count. Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231023094635.1588282-3-zhao1.liu@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> |
||
|
Stefan Hajnoczi
|
17735e9371 |
Hyper-V Dynamic Memory protocol driver.
This driver is like virtio-balloon on steroids for Windows guests: it allows both changing the guest memory allocation via ballooning and inserting pieces of extra RAM into it on demand from a provided memory backend via Windows-native Hyper-V Dynamic Memory protocol. * Preparatory patches to support empty memory devices and ones with large alignment requirements. * Revert of recently added "hw/virtio/virtio-pmem: Replace impossible check by assertion" commit |
||
|
Maciej S. Szmigiero
|
259ebed45a |
qapi: Add HV_BALLOON_STATUS_REPORT event and its QMP query command
Used by the hv-balloon driver for (optional) guest memory status reports. Acked-by: David Hildenbrand <david@redhat.com> Signed-off-by: Maciej S. Szmigiero <maciej.szmigiero@oracle.com> |
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Hyman Huang
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17257b90be |
tests: Add migration dirty-limit capability test
Add migration dirty-limit capability test if kernel support dirty ring. Migration dirty-limit capability introduce dirty limit capability, two parameters: x-vcpu-dirty-limit-period and vcpu-dirty-limit are introduced to implement the live migration with dirty limit. The test case does the following things: 1. start src, dst vm and enable dirty-limit capability 2. start migrate and set cancel it to check if dirty limit stop working. 3. restart dst vm 4. start migrate and enable dirty-limit capability 5. check if migration satisfy the convergence condition during pre-switchover phase. Note that this test case involves many passes, so it runs in slow mode only. Signed-off-by: Hyman Huang <yong.huang@smartx.com> Acked-by: Peter Xu <peterx@redhat.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com> Message-ID: <e55a302df9da7dbc00ad825f47f57c1a756d303e.1698847223.git.yong.huang@smartx.com> |
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Stefan Hajnoczi
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d762bf9793 |
target-arm queue:
* linux-user/elfload: Add missing arm64 hwcap values * stellaris-gamepad: Convert to qdev * docs/specs: Convert various txt docs to rST * MAINTAINERS: Make sure that gicv3_internal.h is covered, too * hw/arm/pxa2xx_gpio: Pass CPU using QOM link property * hw/watchdog/wdt_imx2: Trace MMIO access and timer activity * hw/misc/imx7_snvs: Trace MMIO access * hw/misc/imx6_ccm: Convert DPRINTF to trace events * hw/i2c/pm_smbus: Convert DPRINTF to trace events * target/arm: Enable FEAT_MOPS insns in user-mode emulation * linux-user: Report AArch64 hwcap2 fields above bit 31 * target/arm: Make FEAT_MOPS SET* insns handle Xs == XZR correctly * target/arm: Fix SVE STR increment * hw/char/stm32f2xx_usart: implement TX interrupts * target/arm: Correctly propagate stage 1 BTI guarded bit in a two-stage walk * xlnx-versal-virt: Add AMD/Xilinx TRNG device -----BEGIN PGP SIGNATURE----- iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmVD3hEZHHBldGVyLm1h eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3kuRD/4mLL2DB+yvQJrzSvUlrjfi /orPDrY9xEQ7ln2YpNqc2BZ4wAgh947yk/ae5+lyACQcBhCPiwMyVK1bBscNxkgA 8YPmuugNem/64+IHiKkz6aroqjvC83dUzJ9R5O9ctV70mgrX32YnhXNkkYVI81Ar bEwBznyYeCiy8ZafVxc2m70fiBOlurb6htYYdt7VHsgB0ozK/80UmuFI6exOKt1r oVyYouMaidNV/AoqZBGSKT2UFvFmI57PWN0YQD8CMECLsB/mBE9TEzSvLRdlOB4G qI5hgEJks61qDL6+YMJ+hskxW+D3g3I1WjuyqhKfiAzcKmmTAp1NsiiDtva8yBzX lDUXc6bPomalrKo1SPsooJv9r4uE3hCayDOlR+qM38DL4j2soSd3QIP7dCzERbZx snrD+ZTtgXtomUN8ojbnOK+kClEfURZ+wALbUEXwAh1sBwrKBxaD4ss4lA2esq10 HJPjBJzAWoSmK2DY6GWt2xIa+GvQwdPnxMpHbp3yAddGP7i/lHM0x60q5YpjHV++ DHaZmLBA7L9wcvT1VrwmieJaB+ADcSfkzBz2KznC4usdEY8BiJhjdRAzkqdGZWV5 HKEg8QwMYHg4QRUoZxW/XdtVzdqcjO5pTSUr3HUE+85sum2e9Yee6rybg1W/EWYv 7SnVkD5zG1BU268/p5k6UA== =OgfH -----END PGP SIGNATURE----- Merge tag 'pull-target-arm-20231102' of https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * linux-user/elfload: Add missing arm64 hwcap values * stellaris-gamepad: Convert to qdev * docs/specs: Convert various txt docs to rST * MAINTAINERS: Make sure that gicv3_internal.h is covered, too * hw/arm/pxa2xx_gpio: Pass CPU using QOM link property * hw/watchdog/wdt_imx2: Trace MMIO access and timer activity * hw/misc/imx7_snvs: Trace MMIO access * hw/misc/imx6_ccm: Convert DPRINTF to trace events * hw/i2c/pm_smbus: Convert DPRINTF to trace events * target/arm: Enable FEAT_MOPS insns in user-mode emulation * linux-user: Report AArch64 hwcap2 fields above bit 31 * target/arm: Make FEAT_MOPS SET* insns handle Xs == XZR correctly * target/arm: Fix SVE STR increment * hw/char/stm32f2xx_usart: implement TX interrupts * target/arm: Correctly propagate stage 1 BTI guarded bit in a two-stage walk * xlnx-versal-virt: Add AMD/Xilinx TRNG device * tag 'pull-target-arm-20231102' of https://git.linaro.org/people/pmaydell/qemu-arm: (33 commits) tests/qtest: Introduce tests for AMD/Xilinx Versal TRNG device hw/arm: xlnx-versal-virt: Add AMD/Xilinx TRNG device hw/misc: Introduce AMD/Xilix Versal TRNG device target/arm: Correctly propagate stage 1 BTI guarded bit in a two-stage walk hw/char/stm32f2xx_usart: Add more definitions for CR1 register hw/char/stm32f2xx_usart: Update IRQ when DR is written hw/char/stm32f2xx_usart: Extract common IRQ update code to update_irq() target/arm: Fix SVE STR increment target/arm: Make FEAT_MOPS SET* insns handle Xs == XZR correctly linux-user: Report AArch64 hwcap2 fields above bit 31 target/arm: Enable FEAT_MOPS insns in user-mode emulation hw/i2c/pm_smbus: Convert DPRINTF to trace events hw/misc/imx6_ccm: Convert DPRINTF to trace events hw/misc/imx7_snvs: Trace MMIO access hw/watchdog/wdt_imx2: Trace timer activity hw/watchdog/wdt_imx2: Trace MMIO access hw/arm/pxa2xx_gpio: Pass CPU using QOM link property MAINTAINERS: Make sure that gicv3_internal.h is covered, too docs/specs/vmgenid: Convert to rST docs/specs/vmcoreinfo: Convert to rST ... Conflicts: hw/input/stellaris_input.c The qdev conversion in this pull request ("stellaris-gamepad: Convert to qdev") eliminates the vmstate_register() call that was converted to vmstate_register_any() in the conflicting migration pull request. vmstate_register_any() is no longer necessary now that this device has been converted to qdev, so take this pull request's version of stellaris_gamepad.c over the previous pull request's stellaris_input.c (the file was renamed). Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> |
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Tong Ho
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1c98a821a2 |
tests/qtest: Introduce tests for AMD/Xilinx Versal TRNG device
Signed-off-by: Tong Ho <tong.ho@amd.com> Message-id: 20231031184611.3029156-4-tong.ho@amd.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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Het Gala
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8e3766eefb |
migration: modify test_multifd_tcp_none() to use new QAPI syntax.
modify multifd tcp common test to incorporate the new QAPI syntax defined. Suggested-by: Aravind Retnakaran <aravind.retnakaran@nutanix.com> Signed-off-by: Het Gala <het.gala@nutanix.com> Signed-off-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com> Message-ID: <20231023182053.8711-15-farosas@suse.de> |
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Fabiano Rosas
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7bca2bb7bf |
tests/migration-test: Add a test for postcopy hangs during RECOVER
To do so, create two paired sockets, but make them not providing real data. Feed those fake sockets to src/dst QEMUs for recovery to let them go into RECOVER stage without going out. Test that we can always kick it out and recover again with the right ports. This patch is based on Fabiano's version here: https://lore.kernel.org/r/877cowmdu0.fsf@suse.de Signed-off-by: Fabiano Rosas <farosas@suse.de> [peterx: write commit message, remove case 1, fix bugs, and more] Signed-off-by: Peter Xu <peterx@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com> Message-ID: <20231017202633.296756-4-peterx@redhat.com> |
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Steve Sistare
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e7b428d6bc |
tests/qtest: migration: add reboot mode test
[ Maintainer note: I put the test as flaky because our CI has problems with shared memory. We will remove the flaky bits as soon as we get a solution. ] Signed-off-by: Steve Sistare <steven.sistare@oracle.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com> Message-ID: <1698263069-406971-7-git-send-email-steven.sistare@oracle.com> |
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Stefan Hajnoczi
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235fe6d06e |
ufs-next-pull-request
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Jeuk Kim
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096434fea1 |
hw/ufs: Modify lu.c to share codes with SCSI subsystem
This patch removes the code that ufs-lu was duplicating from scsi-hd and allows them to share code. It makes ufs-lu have a virtual scsi-bus and scsi-hd internally. This allows scsi related commands to be passed thorugh to the scsi-hd. The query request and nop command work the same as the existing logic. Well-known lus do not have a virtual scsi-bus and scsi-hd, and handle the necessary scsi commands by emulating them directly. Signed-off-by: Jeuk Kim <jeuk20.kim@samsung.com> |
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Vladimir Sementsov-Ogievskiy
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1aa84a4b6e |
ipmi-bt-test: force ipv4
We open ipv4 listening socket. But "localhost" in qemu parameters may load to Qemu trying to connect with ipv6 and fail with "Connection refused". Force ipv4 by using ipv4 ip address. Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru> Message-ID: <20231018191123.1176602-1-vsementsov@yandex-team.ru> Acked-by: Corey Minyard <cminyard@mvista.com> Signed-off-by: Thomas Huth <thuth@redhat.com> |