Clarify gdb's register set layout by using constants for
cpu_gdb_read/write_register.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This patch adds support for the vCont remote gdb command. It is used by
gdb 6.8 or better to switch the debugging focus for single-stepping
multi-threaded targets, ie. multi-threaded application in user mode
emulation or VCPUs in system emulation.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This got broken between a13a4126c8 and c92ef6a22d: old slirp code used
255.255.255.0.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Disable the lengthy BIOS prompt for selecting a boot device by default,
but let the user reenable it via '-boot menu=on'.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This allows to specify an exceptional boot order only for the first
startup of the guest. After reboot, qemu will switch back to the default
order (or what was specified via 'order='). Makes installing from CD
images and then booting the freshly set up harddisk more handy.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Will be used by '-boot once=...', and should also help in other use
cases.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Convert the reset handler maintenance code to TAILQ services.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Move registration function for the boot_set callback handler and provide
qemu_boot_set so that it can also be used outside the monitor code.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This patch changes the boot command line option to the canonical format
-boot [order=drives][,...]
where 'drives' is using the same format as the old -boot. The format
switch allows to add the 'menu' and 'once' options in later patches. The
old format is still understood and will be processed at least for a
transition time.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Add a pc-0-10 machine type to allow a pc machine to be created with
virtio block and console devices compatibility with qemu-0.10.x.
Signed-off-by: Mark McLoughlin <markmc@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
We're using PCI_CLASS_DISPLAY_OTHER now, but qemu-kvm.git is using
PCI_CLASS_OTHERS because:
"As a PCI_CLASS_DISPLAY_OTHER, it reduces primary display somehow on
Windows XP (possibly Windows disables acceleration since it fails
to find a driver)."
While this is valid, many versions of X will get confused by it.
Class major number of 0 gets treated as a possibly prehistoric VGA
device, and then the autoconfig logic gets confused trying to figure
out whether the virtio console or the pv vga device are the real VGA.
We should really set a proper class ID. 0x0780 (serial / other) seems
most appropriate. This shouldn't require any kernel changes, the
modalias for virtio looks like:
alias: pci:v00001AF4d*sv*sd*bc*sc*i*
so won't care what the base class or subclass are.
It shows up in the guest as:
00:05.0 Communication controller: Qumranet, Inc. Virtio console
A new qdev type is introduced to allow devices using the old class
to be created for compatibility with qemu-0.10.x.
Reported-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Mark McLoughlin <markmc@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Windows virtio driver cannot pass DTM (certification) tests while the
storage class is PCI_CLASS_STORAGE_UNKNOWN.
A new qdev type is introduced to allow devices using the old class
to be created for compatibility with qemu-0.10.x.
Reported-by: Dor Laor <dlaor@redhat.com>
Signed-off-by: Mark McLoughlin <markmc@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
According to PPC440 user manual, PPC 440 supports ``mftb'' even it's a
preserved instruction:
PPC440_UM2013.pdf, p.445, table A-3
when I compile a kernel (2.6.30, bamboo_defconfig/440EP &
canyonlands/460EX), I can see ``mftb'' by using ppc-xxx-objdump
vmlinux
I have also checked the ppc 440x[456], 460S, 464, they also should support mftb.
The following patch enable mftb for all ppc 440 variants, including:
440EP, 440GP, 440x4, 440x5 and 460
Signed-off-by: Baojun Wang <wangbj@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
The powerpc xml files contained a hack--an empty, non-existent
register--for getting the register numbers to line up for
newer (XML-aware) and older (non-XML-aware) GDB. While this hack worked
in some cases, it didn't work in all cases, notably when the user used
`finish' or `continue': GDB would attempt to read the non-existent
register and QEMU would complain.
This patch fixes things up properly. Instead of inserting a fake
register, we explicitly declare the floating-point and SPE registers to
start at 71. This action accomplishes the same thing as the nasty hack,
except that now GDB never tries to fetch the non-existant register 70.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
For 32-bit PPC targets, we translated:
evmergelo rX, rX, rY
as:
rX-lo = rY-lo
rX-hi = rX-lo
which is wrong, because we should be transferring rX-lo first. This
problem is fixed by swapping the order in which we write the parts of
rX.
Similarly, we translated:
evmergelohi rX, rX, rY
as:
rX-lo = rY-hi
rX-hi = rX-lo
In this case, we can't swap the assignment statements, because that
would just cause problems for:
evmergelohi rX, rY, rX
Instead, we detect the first case and save rX-lo in a temporary
variable:
tmp = rX-lo
rX-lo = rY-hi
rX-hi = tmp
These problems don't occur on PPC64 targets because we don't split the
SPE registers into hi/lo parts for such targets.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Use parameter 'next' to fix the hdecr case.
Also pass 'next' by value instead of pointer (more easy to read and no
performance issue for an always_inline function).
Signed-off-by: Tristan Gingold <gingold@adacore.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Fix botched merge of op_ldst_sc calls to match actual implementation.
Thanks to Aurelien Jarno for diagnosing this.
Signed-off-by: Paul Brook <paul@codesourcery.com>
On Sun, Jul 12, 2009 at 12:09 PM, Blue Swirl<blauwirbel@gmail.com> wrote:
> On 7/12/09, Igor Kovalenko <igor.v.kovalenko@gmail.com> wrote:
>> Good trap handling is required to process interrupts.
>> This patch fixes the following:
>>
>> - sparc64 has no wim register
>> - sparc64 has no psret register, use IE bit of pstate
>> extract IE checking code to cpu_interrupts_enabled
>> - alternate globals are not available if cpu has GL feature
>> in this case bit AG of pstate is constant zero
>> - write to pstate must actually write pstate
>> even if cpu has GL feature
>>
>> Also timer interrupt is handled using do_interrupt.
>
> A bit too much for one patch. Please also remove the code instead of
> commenting out.
I now excluded timer interrupt related part.
To my mind other changes are essentially tied together.
> PUT_PSR for Sparc64 needs CC_OP = CC_OP_FLAGS; like Sparc32.
Fixed, please find attached the updated version.
--
Kind regards,
Igor V. Kovalenko
On Sun, Jul 12, 2009 at 12:43 AM, Stuart Brady<sdbrady@ntlworld.com> wrote:
> On Sat, Jul 11, 2009 at 10:22:18PM +0400, Igor Kovalenko wrote:
>> It is clear that intention is to byte-swap value to be written, not
>> the target address.
>
> @@ -1949,13 +1949,13 @@ void helper_st_asi(target_ulong addr, ta
> case 0x89: // Secondary LE
> switch(size) {
> case 2:
> - addr = bswap16(addr);
> + addr = bswap16(val);
> ^^^^
> Shouldn't that be 'val = bswap16(val)' (and likewise for the 32-bit and
> 64-bit cases)? Also needs a 'signed-off-by:'...
>
> Cheers,
> --
> Stuart Brady
>
Thanks, that part I did not runtime-tested.
Not sure if those asi stores are of any use for user-mode emulator.
Please find attached the corrected version.
Signed-off-by: igor.v.kovalenko@gmail.com
--
Kind regards,
Igor V. Kovalenko
Allocate irq just before passing it to pci bridge initialization
and actually use it to initialize pci bridge.
Signed-off-by: igor.v.kovalenko@gmail.com
--
Kind regards,
Igor V. Kovalenko
This patch extracts common part of sparc64 tag
matching code used by IMMU and DMMU lookups.
Signed-off-by: igor.v.kovalenko@gmail.com
--
Kind regards,
Igor V. Kovalenko
This Implement physical address truncation in mmu bypass mode.
IMMU bypass is also active when cpu enters RED_STATE
Signed-off-by: igor.v.kovalenko@gmail.com
--
Kind regards,
Igor V. Kovalenko
For the sake of consistency. I pulled in the wrong patches from Gerd when
he did the qdev conversion.
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Commit 6a7ad299 ("Call qemu_bh_delete at bdrv_aio_bh_cb") deletes emulated
aio bottom halves to prevent endless accumulation. However, it leaves a
stale ->bh pointer, which is then waited on when the aio is reused.
Zeroing the pointer fixes the issue, allowing vmdk format images to be used.
Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
When we finish migration, there may be pending async io requests
in flight. If we don't flush it before stage3 starting, it might be
the case that the guest loses it.
Signed-off-by: Glauber Costa <glommer@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Allocate enough memory for KVM_GET_MSR_INDEX_LIST as older kernels shot
far beyond their limits, corrupting user space memory.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Usage of msi vectors is controlled by the guest and so needs to be
restored on load. Do this for msi vectors used by the virtio device.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
MSIX present bit is tested incorrectly, and only happens to work because
the bit we are testing is 0x1. Add braces to fix this.
Reported-by: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Clean up msix vector usage state on load. Since guest might have control
over it through the device, the device will have to load this state from
file.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Contrary to what one could expect, the size of L1 tables is not cluster
aligned. So as we're writing whole sectors now instead of single entries,
we need to ensure that the L1 table in memory is large enough; otherwise
write would access memory after the end of the L1 table.
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Jan Kiszka
Anthony Liguori
Mark McLoughlin
Blue Swirl
malc
Baojun Wang
Nathan Froyd
Tristan Gingold
Aurelien Jarno
Paul Brook
Igor Kovalenko
Avi Kivity
Glauber Costa
Jan Kiszka
Michael S. Tsirkin
Kevin Wolf