Commit Graph

5171 Commits

Author SHA1 Message Date
aliguori
c0a04f0e13 Fix up pxe boot (Glauber Costa)
As discussed in
http://lists.gnu.org/archive/html/qemu-devel/2008-08/msg00667.html,
current pxe boot is broken for some use cases. The problem
goes away if we reduce the number of allowed bits in the address space
to 32 (which has the side effect of reducing guest max mem size to 4Gb).

After digging for a while, it turns out that it happens because pxelinux
tries to access address 0x10009e9a6, which does not fit a 32-bit address.
A closer look, however, reveals this access is totally valid: It's just
0x9e9a6 with an add carry.

To avoid this, this patch casts the address passed to the POPL macro to
a 32-bit value. This is also done, although just theorectically, for
PUSHL too.

Signed-off-by: Glauber Costa <glommer@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Reported-by: Chris Lalancette <clalance@redhat.com>
CC: Eduardo Habkost <ehabkost@redhat.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5182 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-09 14:49:02 +00:00
aurel32
c690524ec1 alpha: only print debug information to the log file
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5181 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-07 21:00:01 +00:00
pbrook
733fef0e40 TCG: Use x86-64 zero extension instructions.
Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5180 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-07 18:07:39 +00:00
pbrook
b6d17150af Implement TCG sign extension ops for x86-64.
Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5179 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-07 17:45:15 +00:00
pbrook
4a7f0e0655 Fix libvdeplug link test.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5178 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-07 16:42:53 +00:00
blueswir1
510aba20f0 Fix a typo in fpsub32
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5177 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-06 17:54:01 +00:00
blueswir1
255e1fcb5a Convert most env fields to TCG registers
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5176 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-06 17:51:43 +00:00
blueswir1
47ad35f16a Silence gcc warning about constant overflow
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5175 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-06 17:50:16 +00:00
blueswir1
5f9981c71d Enable gcc flag -Wundef
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5174 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-06 17:49:06 +00:00
blueswir1
eb38c52c2a Fix most warnings that would be caused by gcc flag -Wundef
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5173 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-06 17:47:39 +00:00
aurel32
5bfd5521ff Some little fixes on QEMU
- some vectors can be declared as "const"
- test on CONFIG_VNC_TLS is done for two times while just one is enough.

(Carlo Bramini)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5172 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-06 16:31:30 +00:00
aurel32
29d26d20e5 fix alpha cmovxx instruction
The CMOV instruction is defined by the alpha manual as:

CMOVxx Ra.rq,Rb.rq,Rc.wq !Operate format
CMOVxx Ra.rq,#b.ib,Rc.wq !Operate format

Operation:
IF TEST(Rav, Condition_based_on_Opcode) THEN
Rc ← Rbv

The current qemu behavior inverses Ra and Rb.  This is fixed by this
patch.

Signed-off-by: Tristan Gingold <gingold@adacore.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5171 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-05 19:07:53 +00:00
edgar_igl
980f8a0b39 CRIS: Mask off the cache selection bit after MMU translations.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5170 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-05 17:17:55 +00:00
aurel32
00dbbb03b6 Revert "TCG: enable debug"
This reverts commit 5166, commited by error.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5169 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-05 14:22:24 +00:00
aurel32
7c417963f7 ppc: Convert op_subf to TCG
Replace op_subf with tcg_gen_sub_tl.

Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5168 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-05 14:19:51 +00:00
aurel32
39dd32eed2 ppc: Convert op_add, op_addi to TCG
Replace op_add with tcg_gen_add_tl and op_addi with tcg_gen_addi_tl.

Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5167 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-05 14:19:43 +00:00
aurel32
b24a39fab0 TCG: enable debug
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5166 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-05 14:19:35 +00:00
aurel32
cdcf4e51aa TCG fixes for target-cris
This patch fixes TCG errors reported on the CRIS target when TCG_DEBUG
is enabled.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Acked-by: Edgar E. Iglesias <edgar@axis.com>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5165 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-05 14:19:27 +00:00
aurel32
2fdbad255e TCG fixes for target-mips
This patch fixes TCG errors reported on the MIPS target when TCG_DEBUG
is enabled.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Acked-by: Thiemo Seufer <ths@networkno.de>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5164 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-05 14:19:17 +00:00
pbrook
9507fb52e2 Fix swapped mvz/mvs instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5163 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-05 12:33:31 +00:00
aurel32
489251fa54 ppc: replace op_set_FT0 with tcg_gen_movi_i64
Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5162 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04 20:34:31 +00:00
aurel32
59df7f62a9 alpha: add target-alpha/helper.h (missing from commit r5150)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5161 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04 20:24:14 +00:00
aurel32
bd568f1849 ppc: Convert nip moves to TCG
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5160 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04 18:06:03 +00:00
aurel32
d38ff48941 ppc: remove unused code
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5159 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04 17:16:41 +00:00
aurel32
47e4661cc4 ppc: Convert CRF moves to TCG
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5158 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04 17:06:47 +00:00
aurel32
ec1ac72d9c ppc: fix fpr TCG registers creation
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5157 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04 15:49:12 +00:00
aurel32
a5e26afa61 ppc: Convert FPR moves to TCG
Replace op_{load,store}_fpr with tcg_gen_mov_i64.
Introduce i64 TCG variables cpu_fpr[0..31] and cpu_FT[0..2].

This obsoletes op_template.h for REG > 7.

Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5156 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04 14:43:54 +00:00
aurel32
1d54269590 ppc: Convert Altivec register moves to TCG
Replace op_{load,store}_avr with helpers gen_{load,store}_avr.
Introduce two sets of i64 TCG variables, cpu_avr{h,l}[0..31], and
cpu_AVR{h,l}[0..2].

Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5155 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04 14:43:45 +00:00
aurel32
bd7d9a6d7b ppc: cleanup register types
- use target_ulong for gpr and dyngen registers
- remove ppc_gpr_t type
- define 64-bit dyngen registers for GPE register on 32-bit targets

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5154 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04 05:26:09 +00:00
aurel32
f78fb44e82 ppc: Convert GPR moves to TCG
Replace op_load_gpr_{T0,T1,T2} and op_store_{T0,T1,T2} with tcg_gen_mov_tl.
Introduce TCG variables cpu_gpr[0..31].

For the SPE extension, assure that ppc_gpr_t is only uint64_t for ppc64.
Introduce TCG variables cpu_gprh[0..31] for upper 32 bits on ppc and helpers
gen_{load,store}_gpr64. Based on suggestions by Aurelien, Thiemo and Blue.

Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5153 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04 05:25:47 +00:00
aurel32
4f821e1757 alpha: convert a few more instructions to TCG
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5152 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04 04:36:20 +00:00
aurel32
3761035f2c alpha: directly access ir registers
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5151 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04 04:36:00 +00:00
aurel32
496cb5b921 convert of few alpha insn to TCG
(based on a patch from Tristan Gingold)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5150 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04 04:35:40 +00:00
aurel32
841c26a0c7 hw/pcnet: use qemu_socket.h
(Jan Kiszka)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5149 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04 04:35:20 +00:00
blueswir1
e83ce55068 Implement no-fault loads
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5148 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-03 17:32:10 +00:00
edgar_igl
4487fd349b ETRAX-FS: Add support for DMA channel resets, needed for recent linux kernels.
* Correct numeric value for the RST state.
* Add emulation for reseting a DMA channel.
* Add a few sanity checks.
* Make it compile with debug enabled.



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5147 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-03 14:40:17 +00:00
edgar_igl
b23761f959 CRIS: Avoid a few unecessary steps in the mmu.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5146 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-03 14:31:11 +00:00
edgar_igl
7d5099d5a4 CRIS: Remove redundant code.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5145 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-03 14:30:27 +00:00
ths
04ba529f81 Delete unused variable.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5144 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-02 23:55:28 +00:00
aurel32
f0413473ff [ppc] Convert op_moven_T2_T0 to TCG
Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5143 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-02 23:26:40 +00:00
aurel32
86c581dc80 [ppc] Convert op_reset_T0, op_set_{T0, T1} to TCG
Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5142 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-02 23:26:32 +00:00
aurel32
b2463a64ec SH4: R2D-PLUS FPGA: simply unassigned memory triggering
Use NULL to trigger unassigned memory error on 32-bit accesses instead
of assert(0) as suggested by Blue Swirl.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5141 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-02 23:26:23 +00:00
aurel32
d317b92da0 hw/pcnet.c: windows compile fix
(Eduardo Felipe)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5140 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-02 23:26:13 +00:00
ths
f8a6ec5817 Build fix for gcc-3.3.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5139 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-02 17:39:45 +00:00
blueswir1
b991c38519 Fix sign extension problems with smul and umul (Vince Weaver)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5138 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-02 16:33:23 +00:00
aurel32
e55fd9340e [ppc] Convert op_move_{T1,T2}_T0 to TCG
Attached patch replaces op_move_T1_T0 and op_move_T2_T0 with
tcg_gen_mov_tl.

Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5137 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-02 16:19:05 +00:00
aurel32
02f4f6c24c [ppc] Convert gen_set_{T0,T1} to TCG
The attached patch replaces gen_set_T0 and gen_set_T1 with
tcg_gen_movi_tl.

Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5136 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-02 16:18:55 +00:00
aurel32
89b190a2bb pcnet: add loopback mode emulation
This patch enhances the pcnet NIC emulation with better loopback mode
support, including CRC generation for looped-back packets in "raw" mode.
The patch has practically no impact on the normal RX and TX path.

Successfully tested against an ancient proprietary pcnet driver that
does a lot of hardware checks on boot-up and now works fine over qemu as
well.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5135 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-02 16:18:46 +00:00
aurel32
b319feb72d sh4: Add R2D-PLUS FPGA support.
This adds trivial support for the R2D-PLUS FPGA, mostly just for the
versioning information that the kernel uses for IRL mappings, in addition
to handling the heartbeat and poweroff writes.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5134 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-02 16:18:38 +00:00
aurel32
0fd3ca30c4 sh4: CPU versioning.
Trivial patch adding CPU listing and the ability to do per-subtype
CVR/PVR/PRR values. Presently SH7750R and SH7751R definitions are
provided, as these are the ones in present use in-tree.

The CVR value for SH7751R is intentionally restricted so the kernel
boots, though this will want to be switched to the proper CVR value
once system emulation has sufficiently stabilized.

This also makes it trivial to abstract subtype specific registers like
MMU_PTEA and to set up feature bits in line with the kernel probing for
things like conditionalizing FPU/DSP context.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5133 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-02 16:18:28 +00:00