Commit Graph

62 Commits

Author SHA1 Message Date
Richard Henderson
2ef6175aa7 tcg: Invert the inclusion of helper.h
Rather than include helper.h with N values of GEN_HELPER, include a
secondary file that sets up the macros to include helper.h.  This
minimizes the files that must be rebuilt when changing the macros
for file N.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-05-28 09:33:54 -07:00
Sebastian Huber
16c358e96e target-sparc: Add and use CPU_FEATURE_CASA
The LEON3 processor has support for the CASA instruction which is
normally only available for SPARC V9 processors.  Binutils 2.24
and GCC 4.9 will support this instruction for LEON3.  GCC uses it to
generate C11 atomic operations.

The CAS synthetic instruction uses an ASI of 0x80.  If TARGET_SPARC64 is
not defined use a supervisor data load/store for an ASI of 0x80 in
helper_ld_asi()/helper_st_asi().  The supervisor data load/store was
choosen according to the LEON3 documentation.

The ASI 0x80 is defined in the SPARC V9 manual, Table 12—Address Space
Identifiers (ASIs).  Here we have: 0x80, ASI_PRIMARY, Unrestricted
access, Primary address space.

Tested with the following program:

  #include <assert.h>
  #include <stdatomic.h>

  void test(void)
  {
    atomic_int a;
    int e;
    _Bool b;

    atomic_store(&a, 1);
    e = 1;
    b = atomic_compare_exchange_strong(&a, &e, 2);
    assert(b);
    assert(atomic_load(&a) == 2);

    atomic_store(&a, 3);
    e = 4;
    b = atomic_compare_exchange_strong(&a, &e, 5);
    assert(!b);
    assert(atomic_load(&a) == 3);
  }

Tested also on a NGMP board with a LEON4 processor.

Reviewed-by: Fabien Chouteau <chouteau@adacore.com>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2014-03-12 00:22:01 +00:00
Richard Henderson
f5daeec412 tcg: Remove stray semi-colons from target-*/helper.h
During GEN_HELPER=1, these are actually stray top-level semi-colons
which are technically invalid ISO C, but GCC accepts as an extension.
If we added enough __extension__ markers that we could dare use
-Wpedantic, we'd see

  warning: ISO C does not allow extra ‘;’ outside of a function

This will become a hard error in the next patch, wherein those ; will
appear in the middle of a data structure.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-10 11:43:37 -07:00
Ronald Hecht
d1c36ba707 SPARC LEON power-down support added
Signed-off-by: Ronald Hecht <address@hidden>
Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-23 10:00:43 +00:00
Paolo Bonzini
022c62cbbc exec: move include files to include/exec/
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-12-19 08:31:31 +01:00
Aurelien Jarno
c33b235358 target-sparc: rename helper flags
Rename helper flags to the new ones. This is purely a mechanical change,
it's possible to use better flags by looking at the helpers.

Acked-by: Blue Swirl <blauwirbel@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-28 14:54:24 +01:00
Richard Henderson
a2ea4aa989 target-sparc: Move taddcctv and tsubcctv out of line
The branches around the exception are maintaining an otherwise
unnecessary use of local temps for the cpu destination.

Note that gen_op_t{add,sub}_cc were identical to gen_op_{add,sub}_cc.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07 16:39:33 +00:00
Richard Henderson
c28ae41ecd target-sparc: Move sdivx and udivx out of line
The branches around the exception are maintaining an otherwise
unnecessary use of local temps for the cpu destination.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07 16:39:33 +00:00
Stefan Weil
bc09845431 target-sparc: Add compiler attribute to some functions which don't return
helper_raise_exception does not return, nor does do_unaligned_access.

Cc: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-03-24 13:02:56 +00:00
Blue Swirl
fe8d8f0f1c Sparc: avoid AREG0 for memory access helpers
Make memory access helpers take a parameter for CPUState instead
of relying on global env. Introduce wrappers for load and store ops.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-03-18 12:22:00 +00:00
Fabien Chouteau
96d922a654 Improve "ta 0" shutdown
This patch replace the previous implementation with this simplified and
more complete version (no shutdown when psret == 1).

Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-11-19 11:22:57 +00:00
Richard Henderson
50c796f9d8 target-sparc: Implement FALIGNDATA inline.
This is a relatively simple sequence of shifts.

Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26 14:00:19 -07:00
Richard Henderson
793a137a41 target-sparc: Implement BMASK/BSHUFFLE.
Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26 14:00:19 -07:00
Richard Henderson
add545ab11 target-sparc: Implement ALIGNADDR* inline.
While ALIGNADDR was implemented out-of-line, ALIGNADDRL was not
implemeneted at all.  However, this is a very simple operation
so we're better off doing this inline.

Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26 14:00:19 -07:00
Richard Henderson
2dedf31497 target-sparc: Implement fpack{16,32,fix}.
Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26 14:00:17 -07:00
Richard Henderson
f888300b81 target-sparc: Implement PDIST.
Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26 13:58:48 -07:00
Richard Henderson
445167723d target-sparc: Do exceptions management fully inside the helpers.
This reduces the size of the individual translation blocks, since
we only emit a single call for each FOP rather than three.  In
addition, clear_float_exceptions expands inline to a single byte store.

Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26 13:57:06 -07:00
Richard Henderson
f027c3b192 target-sparc: Make FPU/VIS helpers const when possible.
This also removes the unused ENV parameter from these helpers.

Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26 13:50:45 -07:00
Richard Henderson
03fb8cfc63 target-sparc: Pass float64 parameters instead of dt0/1 temporaries.
Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26 13:50:45 -07:00
Blue Swirl
7a5e4488cd Sparc: avoid AREG0 for division op helpers
Make [su]div{,cc} helpers take a parameter for CPUState instead
of relying on global env. Move the functions to helper.c.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-26 17:18:52 +00:00
Blue Swirl
7922703623 Sparc: avoid AREG0 for softint op helpers and Leon cache control
Make softint op helpers and Leon cache irq manager take a parameter
for CPUState instead of relying on global env. Move the functions
to int{32,64}_helper.c.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-26 17:18:09 +00:00
Blue Swirl
063c367558 Sparc: avoid AREG0 for CWP and PSTATE helpers
Make CWP and PSTATE helpers take a parameter for CPUState instead
of relying on global env. Remove wrapper functions.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-26 17:18:04 +00:00
Blue Swirl
2ffd9176b1 Sparc: avoid AREG0 for lazy condition code helpers
Make lazy condition code helpers take a parameter for CPUState instead
of relying on global env.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-23 15:09:37 +00:00
Blue Swirl
2e2f4ade86 Sparc: avoid AREG0 for float and VIS ops
Make floating point and VIS ops take a parameter for CPUState instead
of relying on global env.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-23 15:09:13 +00:00
Blue Swirl
bc2653195a Sparc: avoid AREG0 for raise_exception and helper_debug
Make raise_exception() and helper_debug() take a parameter for
CPUState instead of relying on global env. Move the functions
to helper.c.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-23 15:08:22 +00:00
Tsuneo Saito
afcb737512 SPARC64: fix VIS1 SIMD signed compare instructions
The destination registers of SIMD signed compare instructions
(fcmp*<16|32>) are not FP registers but general purpose r registers.
Comparisons should be freg_rs1 CMP freg_rs2, that were reversed.

Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-20 20:44:23 +00:00
Blue Swirl
dcfd14b374 Delete unused tb_invalidate_page_range
tb_invalidate_page_range() was intended to be used to invalidate an
area of a TB which the guest explicitly flushes from i-cache. However,
QEMU detects writes to code areas where TBs have been generated, so
his has never been useful.

Delete the function, adjust callers.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-05-22 10:47:28 +00:00
Fabien Chouteau
b04d989054 SPARC: Emulation of Leon3
Leon3 is an open-source VHDL System-On-Chip, well known in space industry (more
information on http://www.gaisler.com).

Leon3 is made of multiple components available in the GrLib VHDL library.
Three devices are implemented: uart, timers and IRQ manager.
You can find code for these peripherals in the grlib_* files.

Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-01-24 20:54:34 +00:00
Aurelien Jarno
0fcec41eec target-sparc: fix udiv(cc) and sdiv(cc)
Since commit 5a4bb580cd, Xorg crashes on
a Debian Etch image. The commit itself is fine, but it triggers a bug
due to wrong computation of flags for udiv(cc) and sdiv(cc).

This patch only compute cc_src2 for the cc version of udiv/sdiv. It
also moves the update of cc_dst and cc_op to the helper, as it is
faster doing it here when there is already an helper.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-12-28 18:44:51 +00:00
Richard Henderson
70c482852a target-sparc: Inline some generation of carry for ADDX/SUBX.
Computing carry is trivial for some inputs.  By avoiding an
external function call, we generate near-optimal code for
the common cases of add+addx (double-word arithmetic) and
cmp+addx (a setcc pattern).

Signed-off-by: Richard Henderson <rth@twiddle.net>
Acked-by: Artyom Tarasenko <atar4qemu@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-05-20 19:58:28 +00:00
Richard Henderson
4c1a0d8244 target-sparc: Fix compilation with --enable-debug.
Return a target_ulong from compute_C_icc to match the width of the users.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-05-19 19:03:33 +00:00
Igor V. Kovalenko
1fae7b705f sparc64: use helper_wrpil to check pending irq on write
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-01-08 17:14:11 +00:00
Blue Swirl
8393617c1a Use dynamical computation for condition codes
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-05-10 07:19:11 +00:00
pbrook
a7812ae412 TCG variable type checking.
Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-17 14:43:54 +00:00
blueswir1
b158a785d2 Implement UA2005 hypervisor traps
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5327 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-26 18:05:23 +00:00
blueswir1
9d92659858 Add software and timer interrupt support
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5299 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-22 19:50:28 +00:00
blueswir1
a7ec422912 Use the new concat_i32_i64 op for std and stda
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5281 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-21 14:49:09 +00:00
blueswir1
d84763bc17 Convert rest of ops using float32 to TCG, remove FT0 and FT1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5193 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-10 20:09:22 +00:00
blueswir1
c5d04e99f3 Partially convert float128 conversion ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5192 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-10 20:00:18 +00:00
blueswir1
e2ea21b396 Convert basic 64 bit VIS ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5191 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-10 19:57:35 +00:00
blueswir1
1d01299d29 Convert basic 32 bit VIS ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5190 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-10 19:57:13 +00:00
blueswir1
714547bbc7 Convert basic float32 ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5189 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-10 19:54:51 +00:00
blueswir1
3a3b925d47 Implement ldxfsr/stxfsr, fix ld(x)fsr masks, convert to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5185 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-09 19:02:49 +00:00
blueswir1
91736d378b Fix Sparc64 boot on i386 host:
- move do_interrupt() back to op_helper.c
 - move non-helper prototypes from helper.h to exec.h
 - move some prototypes from cpu.h to exec.h
 - do not export either set_cwp() or cpu_set_cwp() from op_helper.c,
   but instead provide inline functions


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5109 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-29 20:50:21 +00:00
blueswir1
db166940e2 Implement nucleus quad ldda
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4902 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-19 13:25:28 +00:00
blueswir1
f2bc7e7fa1 Move non-op functions from op_helper.c to helper.c and vice versa.
Rearrange interrupt handling to match other targets.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4590 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-27 17:35:30 +00:00
blueswir1
c9e03d8f68 Register op helpers
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4534 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-22 18:16:25 +00:00
blueswir1
4da450e616 Move prototype back to avoid a compiler warning
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4443 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-12 17:59:14 +00:00
blueswir1
22548760ca Fix compiler warnings
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4404 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-10 10:12:00 +00:00
blueswir1
64a88d5d3a CPU feature selection support
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4399 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-09 20:13:43 +00:00