OpenE2K
/
qemu-e2k
13
4
Fork 0
Code Issues 4 Pull Requests Projects 2 Releases Activity
4,949 Commits 10 Branches 0 Tags 459 MiB
Commit Graph

16 Commits

Author SHA1 Message Date
malc e46b9681e5 Provide extNs_M instructions 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4934 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-23 20:01:23 +00:00
malc e924c48573 Fuse EQ and NE handling in tcg_out_brcond2 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4845 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-03 23:49:14 +00:00
malc 8c5e95d807 Mask LL portion of B to 24 bits in tcg_out_b (Thanks to Thiemo Seufer) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4841 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-03 18:51:23 +00:00
malc ca88500f43 According to gcc-4.3.0/gcc/config/rs6000/crtsavres.asm R13 is volatile 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4779 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-23 05:47:06 +00:00
malc a35e86c55f Shuffle contents of tcg_target_reg_alloc_order 
Move reserved/volatile registers down. Currently qemu_ld/stXX are
marked with TCG_OPF_CALL_CLOBBER and since memory accesses are
frequent and R3 through R12 are volatile moving this down results in
less spills and tighter generated code.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4778 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-23 05:47:03 +00:00
malc 17ca26e791 Save LR into proper place on callers stack frame 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4745 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-18 01:58:52 +00:00
malc c596defdb9 Reimplement brcond2 and refactor brcond 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4738 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-12 12:33:10 +00:00
malc 0d5bd3631f Remove stray variable 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4725 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-10 01:47:17 +00:00
malc 77b73de676 Use rem/div[u]_i32 drop div[u]2_i32 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4722 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-09 23:44:44 +00:00
malc fa4fbfb98a Emit trampolines manually in prologue 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4715 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-09 19:57:36 +00:00
malc 5d794885a2 Fix test for signed div fast path 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4714 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-09 19:57:27 +00:00
malc 398ce98e4f Fix div[u]2. 
Previous code assummed 32 by 32 bit divmod operation, and survived
x86_64 test only by sheer luck. MIPS wasn't so forgiving.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4705 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-09 06:06:25 +00:00
malc 0a878c4760 PPC TCG Fixes 
* Fix typo in aliased div2
* "Optimize" aliased div2/divu2
* Fix two remaining branch retranslation problems
  (Kudos to Andrzej Zaborowski)
* Rework goto_tb and set_jmp_target1
* Use correct size when flushing icache
* Use correct register selection for ORI
  (Was harmless since in both cases srcreg was equal to dstreg)



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4691 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-07 20:31:33 +00:00
bellard 932a690969 support of long calls for PPC (malc) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4629 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-30 20:56:52 +00:00
bellard f3f478a7ef Fix signed/unsigned issues of immediate version of brcond (malc) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4588 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-26 19:11:07 +00:00
bellard 2662e13f68 ppc TCG target (malc) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4584 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-25 18:59:57 +00:00