Commit Graph

53 Commits

Author SHA1 Message Date
Andreas Färber f54d31575d ioapic: QOM cast cleanup
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29 21:07:02 +02:00
Andreas Färber cc3e064ee9 xilinx_intc: QOM cast cleanup
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29 21:06:58 +02:00
Andreas Färber 7abad863d7 slavio_intctl: QOM cast cleanup
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29 21:06:58 +02:00
Andreas Färber b09a6f7b30 realview_gic: QOM cast cleanup
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29 21:06:58 +02:00
Andreas Färber 1ecdf4022a puv3_intc: QOM cast cleanup
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29 21:06:58 +02:00
Andreas Färber 7fc3266f76 pl190: QOM cast cleanup
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29 21:06:58 +02:00
Andreas Färber aefbc25695 pl190: Rename pl190_state to PL190State
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29 21:06:58 +02:00
Andreas Färber 47edc5a479 omap_intc: QOM'ify omap-intc and omap2-intc
Create a new abstract base type and let omap-intc and omap2-intc inherit
from it. Introduce a type constant and use QOM casts.

Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29 21:06:58 +02:00
Andreas Färber 1f8a9eac51 lm32_pic: QOM cast cleanup
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29 21:06:57 +02:00
Andreas Färber 730bf9323d grlib_irqmp: QOM cast cleanup
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29 21:06:57 +02:00
Andreas Färber c5e22ae346 exynos4210_gic: QOM cast cleanup for exynos4210.irq_gate
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29 21:06:57 +02:00
Andreas Färber 78c6abbd83 exynos4210_gic: QOM cast cleanup for exynos4210.gic
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29 21:06:57 +02:00
Andreas Färber c03c6b9cca exynos4210_combiner: QOM cast cleanup
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29 21:06:57 +02:00
Andreas Färber 9062143f9e etraxfs_pic: QOM cast cleanup
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29 21:06:57 +02:00
Andreas Färber 285b4432da arm_gic: QOM cast cleanup
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29 21:06:57 +02:00
Andreas Färber 5ff94a61c4 imx_avic: QOM cast cleanup
Introduce type constant, use QOM casts and prepare SysBus initfn for QOM
realize by resolving SysBusDevice vs. DeviceState "dev" name conflict.

Acked-by: Peter Chubb <peter.chubb@nicta.com.au>
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29 21:06:05 +02:00
Anthony Liguori c04d6cfa3f xics: rename types to be sane and follow coding style
Basically, in HW the layout of the interrupt network is:

     - One ICP per processor thread (the "presenter"). This contains the
    registers to fetch a pending interrupt (ack), EOI, and control the
    processor priority.

     - One ICS per logical source of interrupts (ie, one per PCI host
    bridge, and a few others here or there). This contains the per-interrupt
    source configuration (target processor(s), priority, mask) and the
    per-interrupt internal state.

    Under PAPR, there is a single "virtual" ICS ... somewhat (it's a bit
    oddball what pHyp does here, arguably there are two but we can ignore
    that distinction). There is no register level access. A pair of firmware
    (RTAS) calls is used to configure each virtual interrupt.

    So our model here is somewhat the same. We have one ICS in the emulated
    XICS which arguably *is* the emulated XICS, there's no point making it a
    separate "device", that would just be gross, and each VCPU has an
    associated ICP.

Yet we call the "XICS" struct icp_state and then the ICPs
'struct icp_server_state'.  It's particularly confusing when all of the
functions have xics_prefixes yet take *icp arguments.

Rename:

  struct icp_state -> XICSState
  struct icp_server_state -> ICPState
  struct ics_state -> ICSState
  struct ics_irq_state -> ICSIRQState

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Message-id: 1374175984-8930-12-git-send-email-aliguori@us.ibm.com
[aik: added ics_resend() on post_load]
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-29 10:37:09 -05:00
Hu Tao f5ba752371 ioapic: Use QOM realize for ioapic
Signed-off-by: Hu Tao <hutao@cn.fujitsu.com>
[AF: Tweaked error message]
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-23 00:37:35 +02:00
Alexey Kardashevskiy 42e5b4c988 pseries: move interrupt controllers to hw/intc/
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-11 18:51:23 +02:00
Andreas Färber 2b927571cc intc/openpic: Build openpic only once
Since current_cpu is CPUState it no longer depends on CPUPPCState.

Move ppce500_set_mpic_proxy() to a new hw/ppc/ppc_e500.h because
hw/ppc/ppc.h is too heavily using CPUPPCState and PowerPCCPU.

Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-09 21:33:02 +02:00
Andreas Färber dfc080791d intc/arm_gic: Build arm_gic only once
Since current_cpu is CPUState it no longer needs CPUArchState.

Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-09 21:33:02 +02:00
Andreas Färber 182735efaf cpu: Make first_cpu and next_cpu CPUState
Move next_cpu from CPU_COMMON to CPUState.
Move first_cpu variable to qom/cpu.h.

gdbstub needs to use CPUState::env_ptr for now.
cpu_copy() no longer needs to save and restore cpu_next.

Acked-by: Paolo Bonzini <pbonzini@redhat.com>
[AF: Rebased, simplified cpu_copy()]
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-09 21:32:54 +02:00
Andreas Färber 4917cf4432 cpu: Replace cpu_single_env with CPUState current_cpu
Move it to qom/cpu.h.

Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-09 21:20:28 +02:00
Paolo Bonzini 1437c94b26 hw/i*: pass owner to memory_region_init* functions
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-07-04 17:42:48 +02:00
Paolo Bonzini 2c9b15cab1 memory: add owner argument to initialization functions
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-07-04 17:42:44 +02:00
Andreas Färber dd49c038c3 intc/openpic_kvm: Fix QOM and build issues
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-01 01:11:15 +02:00
Andreas Färber cbe72019b1 intc/openpic: Convert to QOM realize
Split qdev initfn into instance_init and realize functions.
Change one occurrence of "klass" while at it.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-01 01:11:15 +02:00
Andreas Färber e1766344fd intc/openpic: QOM'ify
Introduce type constant and cast macro.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-01 01:11:14 +02:00
Scott Wood d85937e683 kvm/openpic: in-kernel mpic support
Enables support for the in-kernel MPIC that thas been merged into the
KVM next branch.  This includes irqfd/KVM_IRQ_LINE support from Alex
Graf (along with some other improvements).

Note from Alex regarding kvm_irqchip_create():

  On x86, one would call kvm_irqchip_create() to initialize an
  in-kernel interrupt controller.  That function then goes ahead and
  initializes global capability variables as well as the default irq
  routing table.

  On ppc, we can't call kvm_irqchip_create() because we can have
  different types of interrupt controllers.  So we want to do all the
  things that function would do for us in the in-kernel device init
  handler.

Signed-off-by: Scott Wood <scottwood@freescale.com>
[agraf: squash in kvm_irqchip_commit_routes patch, fix non-kvm build,
        fix ppcemb]
Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-01 01:11:14 +02:00
Scott Wood 8935a442cd openpic: factor out some common defines into openpic.h
...for use by the KVM in-kernel irqchip stub.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-01 01:11:14 +02:00
Peter Crosthwaite afd59989db intc/xilinx_intc: Dont lower IRQ when HIE cleared
This is a little strange. It is lowering the parent IRQ pin on input
when HIE is cleared. There is no such behaviour in the real hardware.

ISR changes based on interrupt pin state are already guarded on HIE
being set. So we can just delete this if in its entirety.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2013-06-18 09:45:00 +02:00
Peter Crosthwaite fa96d6142f intc/xilinx_intc: Inhibit write to ISR when HIE
When the Hardware Interrupt Enable (HIE) bit is set, software cannot
change ISR. Add write guard accordingly.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2013-06-18 09:45:00 +02:00
Peter Crosthwaite 45fdd3bf5a intc/xilinx_intc: Handle level interrupt retriggering
Acking a level sensitive interrupt should have no effect if the
interrupt pin is still asserted. The current implementation requires
and edge condition to occur for setting a level sensitive IRQ, which
means an ACK can clear a level sensitive interrupt, until the original
source strobes the interrupt again.

Fix by keeping track of the interrupt pin state and setting ISR based
on this every time update_irq() is called.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2013-06-18 09:45:00 +02:00
Peter Crosthwaite 6327c221ff intc/xilinx_intc: Don't clear level sens. IRQs without ACK
For level sensitive interrupts, ISR bits are cleared when the input pin
is lowered. This is incorrect. Only software can clear ISR bits (via
IAR or direct write to ISR with !MER(2)).

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2013-06-18 09:44:59 +02:00
Blue Swirl 371a775dc1 Merge branch 'realize-isa.v2' of git://github.com/afaerber/qemu-cpu
* 'realize-isa.v2' of git://github.com/afaerber/qemu-cpu:
  qdev: Drop FROM_QBUS() macro
  isa: QOM'ify ISADevice
  isa: QOM'ify ISABus
  i8259: Convert PICCommonState to use QOM realizefn
  kvm/i8259: QOM'ify some more
  i8259: QOM'ify some more
  i8254: Convert PITCommonState to QOM realizefn
  kvm/i8254: QOM'ify some more
  i8254: QOM'ify some more
  isa: Use realizefn for ISADevice
  cs4231a: QOM'ify some more
  gus: QOM'ify some more
2013-06-15 10:53:44 +00:00
Peter Crosthwaite 5c9f43363a intc/xilinx_intc: Use qemu_set_irq
Use qemu_set_irq rather than if-elsing qemu_irq_(lower|raise). No
functional change, just reduces verbosity.

Cc: qemu-trivial@nongnu.org

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2013-06-11 23:45:43 +04:00
Andreas Färber 4a17cc4f28 isa: QOM'ify ISADevice
Rename its parent field and use DEVICE() where necessary.

Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-06-07 14:55:33 +02:00
Andreas Färber d2628b7d18 i8259: Convert PICCommonState to use QOM realizefn
Instead of having the parent provide PICCommonClass::init,
let the children override DeviceClass::realize themselves.
This pushes the responsibility of saving and calling the parent's
realizefn to the children.

Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-06-07 14:55:24 +02:00
Andreas Färber d1eebf4e3d i8259: QOM'ify some more
Introduce type constant.

Prepares for PIC realizefn.

Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-06-07 14:55:24 +02:00
Andreas Färber db895a1e6a isa: Use realizefn for ISADevice
Drop ISADeviceClass::init and the resulting no-op initfn and let
children implement their own realizefn. Adapt error handling.
Split off an instance_init where sensible.

Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-06-07 12:14:45 +02:00
Michael S. Tsirkin edf9735e40 apic: rename apic specific bitopts
apic has its own version of bitops, with the
difference that it works on u32 and not long.
Add apic_ prefix to avoid namespace clashes.

We should look into reusing standard bitops long-term,
but that's not entirely trivial.

Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-06-02 18:14:02 +03:00
Blue Swirl 6a4e177114 Remove Sun4c, Sun4d and a few CPUs
Sun4c and Sun4d architectures and related CPUs are not fully implemented
(especially Sun4c MMU) and there has been no interest for them.

Likewise, a few CPUs (Cypress, Ross etc) are only half implemented.

Remove the machines and CPUs, they can be re-added if needed later.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-05-26 11:37:58 +00:00
Dong Xu Wang c7e775e4dd remove double semicolons
Signed-off-by: Dong Xu Wang <wdongxu@linux.vnet.ibm.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2013-05-12 13:25:55 +04:00
Igor Mammedov 53a89e262b target-i386: Move APIC to ICC bus
It allows APIC to be hotplugged.

 * map APIC's mmio at board level if it is present
 * do not register mmio region for each APIC, since
   only one is used/mapped

Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-05-01 13:06:07 +02:00
Igor Mammedov baaeda08ff target-i386: Replace MSI_SPACE_SIZE with APIC_SPACE_SIZE
Put APIC_SPACE_SIZE in a public header so that it can be
reused elsewhere later.

Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-05-01 13:04:19 +02:00
Andreas Färber 29bb5317cb i8259: QOM cleanups
Eliminate DO_UPCAST() for PICCommonState. Prepares for ISA realizefn.

Also give the i8259_common type registration functions unique names
while at it.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Message-id: 1367093935-29091-6-git-send-email-afaerber@suse.de
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-04-29 08:27:47 -05:00
Igor Mammedov f16a69f7fc ioapic: Replace FROM_SYSBUS() with QOM type cast
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-04-16 01:19:46 +02:00
Peter Maydell bd2be15003 arm: fix location of some include files
The recent rearrangement of include files had some minor errors:
 devices.h is not ARM specific and should not be in arm/
 arm.h should be in arm/

Move these two headers to correct this.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-04-15 15:16:01 +02:00
Peter Maydell e03ba13637 Typo, spelling and grammatical fixes
Minor fixes to documentation and code comments.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2013-04-12 14:33:20 +02:00
Paolo Bonzini 47b43a1f41 hw: move private headers to hw/ subdirectories.
Many headers are used only in a single directory.  These can be
kept in hw/.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-04-08 18:13:16 +02:00