Commit Graph

527 Commits

Author SHA1 Message Date
Blue Swirl b55a37c981 user: move CPU reset call to main.c for x86/PPC/Sparc
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-11-07 10:37:06 +00:00
Glauber Costa c169998802 v3: don't call reset functions on cpu initialization
There is absolutely no need to call reset functions when initializing
devices. Since we are already registering them, calling qemu_system_reset()
should suffice. Actually, it is what happens when we reboot the machine,
and using the same process instead of a special case semantics will even
allow us to find bugs easier.

Furthermore, the fact that we initialize things like the cpu quite early,
leads to the need to introduce synchronization stuff like qemu_system_cond.
This patch removes it entirely. All we need to do is call qemu_system_reset()
only when we're already sure the system is up and running

I tested it with qemu (with and without io-thread) and qemu-kvm, and it
seems to be doing okay - although qemu-kvm uses a slightly different patch.

[ v2: user mode still needs cpu_reset, so put it in ifdef. ]
[ v3: leave qemu_system_cond for now. ]

Signed-off-by: Glauber Costa <glommer@redhat.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-11-07 08:06:58 +00:00
Juan Quintela d4829d4992 vmstate: Add version arg to VMSTATE_SINGLE_TEST()
This allows to define VMSTATE_SINGLE with VMSTATE_SINGLE_TEST
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-27 12:28:51 -05:00
Andre Przywara 31501a714b target-i386: implement lzcnt emulation
lzcnt is a AMD Phenom/Barcelona added instruction returning the
number of leading zero bits in a word.
As this is similar to the "bsr" instruction, reuse the existing
code. There need to be some more changes, though, as lzcnt always
returns a valid value (in opposite to bsr, which has a special
case when the operand is 0).
lzcnt is guarded by the ABM CPUID bit (Fn8000_0001:ECX_5).

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-23 17:10:36 +02:00
Blue Swirl 976b2037e5 x86: add 'static' to please Sparse
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-10-18 14:51:10 +00:00
Laurent Desnogues 49d9fdcca6 target-i386: fix ARPL
The arpl implementation in target-i386/translate.c uses cpu_A0
temporary across a brcond op.  This patch fixes that issue.

Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-06 22:01:00 +02:00
Aurelien Jarno 5a2d0e57ad target-i386: move recently added vmstate fields at the end of the structure
This reduce the impact on hosts that have addressing modes with limited
offsets. Suggested by Laurent Desnogues.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-05 22:41:04 +02:00
Juan Quintela 1e7fbc6d3c x86: fix miss merge
There was a missmerge, and then we got a tail recursive call to cpu_post_load
without case base :)

Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 14:01:16 -05:00
Jan Kiszka 5f30fa18ad gdbstub: x86: Switch 64/32 bit registers dynamically
Commit 56aebc8916 changed gdbstub in way
that debugging 32 or 16-bit guest code is no longer possible with qemu
for x86_64 guest CPUs. Since that commit, qemu only provides registers
sets for 64-bit, forcing current and foreseeable gdb to also switch its
architecture to 64-bit. And this breaks if the inferior is 32 or 16 bit.

No question, this is a gdb issue. But, as it was confirmed in several
discusssions with gdb people, it is a non-trivial thing to fix. So until
qemu finds a gdb version attach with a rework x86 support, we have to
work around it by switching the register layout as the guest switches
its execution mode between 16/32 and 64 bit.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:45 -05:00
Juan Quintela 0cb892aa26 x86: port cpu to vmstate
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:43 -05:00
Juan Quintela 3c8ce630c5 x86: factor out cpu_get/put_fpreg()
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:43 -05:00
Juan Quintela 216c07c3a8 x86: factor out cpu_get/put_mttr_var()
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:42 -05:00
Juan Quintela fc3b0aa23e x86: factor out cpu_get/put_xmm_reg()
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:42 -05:00
Juan Quintela 468f65814e x86: factor out cpu_pre/post_load()
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:42 -05:00
Juan Quintela c4c38c8c72 x86: factor out cpu_pre_save()
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:42 -05:00
Juan Quintela 66e6d55b75 x86: port segments to vmstate
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:42 -05:00
Juan Quintela c1a54d573b x86: split MTRRVar union
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:42 -05:00
Juan Quintela acc6883679 x86: split FPReg union
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:42 -05:00
Juan Quintela e5cc6429de x86: mcg_cap is never 0
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:42 -05:00
Juan Quintela 496eb021d8 x86: send mce_banks as an array
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:41 -05:00
Juan Quintela ac74d0f1fc x86: mce_banks always have the same size
mce_banks is always MCE_BANKS_DEF * 4 in size, value never change

CC: Huang Ying <ying.huang@intel.com>
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:41 -05:00
Juan Quintela 60a902f1c3 x86: add fpregs_format_vmstate
Don't even ask, being able to load/save between 64<->80bit floats should be forbidden

Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:41 -05:00
Juan Quintela bfc179b60c x86: add pending_irq_vmstate to the state
It is needed to save the interrupt_bitmap

Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:40 -05:00
Juan Quintela cdc0c58fa9 x86: add fptag_vmstate to the state
It is needed to store fptags

Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:40 -05:00
Juan Quintela 67b8f41957 x86: fpus is uint16_t not unsigned int
We save more that fpus on that 16 bits (fpstt), we need an additional field

Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:40 -05:00
Juan Quintela eb83162311 x86: fpuc is uint16_t not unsigned int
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:40 -05:00
Juan Quintela 5ee0ffaa42 x86: make a20_mask int32_t
This makes the savevm code correct, and sign extensins gives us exactly
what we need (namely, sign extend to 64 bits when used with 64bit addresess.

Once there, change 0x100000 for 1 << 20, that maks all a20 use the same syntax.

Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:39 -05:00
Juan Quintela 1f76b9b9b3 x86: hflags is not modified at all, just save it directly
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:39 -05:00
Kevin Wolf 09d85fb843 target-i386: Fix exceptions for fxsave/fxrstor
This patch corrects the following aspects of exception generation in
fxsave/fxrstor:

* Generate #GP if the operand is not aligned to a 16 byte boundary
* Generate #UD if the LOCK prefix is used
* For CR0.EM = 1 #NM is generated, not #UD

Signed-off-by: Kevin Wolf <mail@kevin-wolf.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-04 23:10:22 +02:00
Andre Przywara 1b050077d2 target-i386: add RDTSCP support
RDTSCP reads the time stamp counter and atomically also the content
of a 32-bit MSR, which can be freely set by the OS. This allows CPU
local data to be queried by userspace.
Linux uses this to allow a fast implementation of the getcpu()
syscall, which uses the vsyscall page to avoid a context switch.
AMD CPUs since K8RevF and Intel CPUs since Nehalem support this
instruction.
RDTSCP is guarded by the RDTSCP CPUID bit (Fn8000_0001:EDX[27]).

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-04 14:46:34 +02:00
Andre Przywara d9f4bb27db target-i386: add SSE4a instruction support
This adds support for the AMD Phenom/Barcelona's SSE4a instructions.
Those include insertq and extrq, which are doing shift and mask on
XMM registers, in two versions (immediate shift/length values and
stored in another XMM register).
Additionally it implements movntss, movntsd, which are scalar
non-temporal stores (avoiding cache trashing). These are implemented
as normal stores, though.
SSE4a is guarded by the SSE4A CPUID bit (Fn8000_0001:ECX[6]).

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-04 14:09:41 +02:00
Andre Przywara ccd59d09a9 target-i386: add lock mov cr0 = cr8
AMD CPUs featuring a shortcut to access CR8 even from 32-bit mode.
If you use the LOCK prefix with "mov CR0", it accesses CR8 instead.
This behavior is guarded by the CR8_LEGACY CPUID bit
(Fn8000_0001:ECX[1]).

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-04 14:04:40 +02:00
Anthony Liguori c227f0995e Revert "Get rid of _t suffix"
In the very least, a change like this requires discussion on the list.

The naming convention is goofy and it causes a massive merge problem.  Something
like this _must_ be presented on the list first so people can provide input
and cope with it.

This reverts commit 99a0949b72.

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-01 16:12:16 -05:00
malc 99a0949b72 Get rid of _t suffix
Some not so obvious bits, slirp and Xen were left alone for the time
being.

Signed-off-by: malc <av1474@comtv.ru>
2009-10-01 22:45:02 +04:00
Laurent Desnogues cc739bb0c4 x86: use globals for CPU registers
Use globals for the 8 or 16 CPU registers on i386 and x86_64.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-30 22:53:05 +02:00
Aurelien Jarno bedda79c1e target-i386: kill a tmp register
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-27 00:57:41 +02:00
Aurelien Jarno 5b207c007c target-i386: use subfi instead of sub with a non-freed constant
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-27 00:57:28 +02:00
Juan Quintela 3897293825 gcc wants 1st static and then const
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-09-25 19:52:06 +00:00
Blue Swirl afcea8cbde ioports: remove unused env parameter and compile only once
The CPU state parameter is not used, remove it and adjust callers. Now we
can compile ioport.c once for all targets.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-09-20 16:05:47 +00:00
Jan Kiszka 2305411129 i386: Drop redundant kvm_enabled test
cpu_synchronize_state already does this.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-09-12 15:52:13 +00:00
Blue Swirl aba1d00a41 Work around OpenSolaris sys/regset.h namespace pollution
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-09-12 12:36:11 +00:00
Blue Swirl 72cf2d4f0e Fix sys-queue.h conflict for good
Problem: Our file sys-queue.h is a copy of the BSD file, but there are
some additions and it's not entirely compatible. Because of that, there have
been conflicts with system headers on BSD systems. Some hacks have been
introduced in the commits 15cc923584,
f40d753718,
96555a96d7 and
3990d09adf but the fixes were fragile.

Solution: Avoid the conflict entirely by renaming the functions and the
file. Revert the previous hacks.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-09-12 07:36:22 +00:00
Gleb Natapov 2637c754cc kvm_arch_get_registers() shouldn't be called directly
Direct call to kvm_arch_get_registers() bypass logic in
cpu_synchronize_state()

Signed-off-by: Gleb Natapov <gleb@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-09-11 11:10:09 -05:00
Blue Swirl 1e6eec8b33 Fix Sparse warnings: add "static"
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-09-05 10:14:07 +00:00
Avi Kivity 4c0960c0c4 kvm: Simplify cpu_synchronize_state()
cpu_synchronize_state() is a little unreadable since the 'modified'
argument isn't self-explanatory.  Simplify it by making it always
synchronize the kernel state into qemu, and automatically flush the
registers back to the kernel if they've been synchronized on this
exit.

Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-08-27 20:35:30 -05:00
Andre Przywara d1cd4bf419 introduce kvm64 CPU
In addition to the TCG based qemu64 type let's introduce a kvm64 CPU type,
which is the least common denominator of all KVM-capable x86-CPUs
(based on Intel Pentium 4 Prescott). It can be used as a base type
for migration.

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-08-27 19:33:15 -05:00
Andre Przywara a8a358bf35 allow overriding of CPUID level on command line
The CPUID level determines how many CPUID leafs are exposed to the guest.
Some features (like multi-core) cannot be propagated without the proper
level, but guests maybe confused by bogus entries in some leafs.
So add level= and xlevel= to the list of -cpu options to allow the user to
override the default settings. While at it, merge unnecessary local
variables into one and allow hexadecimal arguments.

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-08-27 19:33:15 -05:00
Andre Przywara 400281af34 set CPUID bits to present cores and threads topology
Controlled by the enhanced -smp option set the CPUID bits to present the
guest the desired topology. This is vendor specific, but (with the exception
of the CMP_LEGACY bit) not conflicting, so we set all bits everytime.
There is no real multithreading support for AMD CPUs, so report cores
instead.

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-08-27 19:33:15 -05:00
Andre Przywara ac72472b5f push CPUID level to 4 to allow Intel multicore decoding
Intel CPUs store the number of cores in CPUID leaf 4. So push
the maxleaf value to 4 to allow the guests access to this leaf.

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-08-27 19:33:15 -05:00
Nathan Froyd 0b5c1ce846 cleanup cpu-exec.c, part 0/N: consolidate handle_cpu_signal
handle_cpu_signal is very nearly copy-paste code for each target, with a
few minor variations.  This patch sets up appropriate defaults for a
generic handle_cpu_signal and provides overrides for particular targets
that did things differently.  Fixing things like the persistent (XXX:
use sigsetjmp) should now become somewhat easier.

Previous comments on this patch suggest that the "activate soft MMU for
this block" comments refer to defunct functionality.  I have removed
such blocks for the appropriate targets in this patch.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-08-24 08:21:42 -05:00