Commit Graph

49 Commits

Author SHA1 Message Date
Richard Henderson
463230d85e tcg-ia64: Introduce tcg_opc_bswap64_i
Acked-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-11-18 15:57:59 +10:00
Richard Henderson
db008a8de2 tcg-ia64: Introduce tcg_opc_ext_i
Being able to "extend" from 64-bits (with a mov) simplifies
a few places where the conditional breaks the train of thought.

Acked-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-11-18 15:57:54 +10:00
Richard Henderson
fa0cdb6c2a tcg-ia64: Introduce tcg_opc_movi_a
Acked-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-11-18 15:57:50 +10:00
Richard Henderson
3b9ccdcc74 tcg-ia64: Introduce tcg_opc_mov_a
Acked-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-11-18 15:57:46 +10:00
Richard Henderson
25c9c73bdc tcg-ia64: Use A3 form of logical operations
We can and/or/xor/andcm small constants, saving one cycle.

Acked-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-11-18 15:57:40 +10:00
Richard Henderson
f940fb086c tcg-ia64: Use SUB_A3 and ADDS_A4 for subtraction
We can subtract from more small constants that just 0 with one insn,
and we can add the negative for most small constants.

Acked-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-11-18 15:57:33 +10:00
Richard Henderson
8642088a3d tcg-ia64: Use ADDS for small addition
Avoids a wasted cycle loading up small constants.

Simplify the code assuming the tcg optimizer is going to work
and don't expect the first operand of the add to be constant.

Acked-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-11-18 15:57:23 +10:00
Richard Henderson
3c289cba9b tcg-ia64: Avoid unnecessary stop bit in tcg_out_alu
When performing an operation with two input registers, we'd leave
the stop bit (and thus an extra cycle) that's only needed when one
or the other input is a constant.

Acked-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-11-18 15:57:16 +10:00
Richard Henderson
d15de15ca0 tcg-ia64: Move AREG0 to R32
Since the move away from the global areg0, we're no longer globally
reserving areg0.  Which means our use of R7 clobbers a call-saved
register.  Shift areg0 into the windowed registers.  Indeed, choose
the incoming parameter register that it comes to us by.

This requires moving the register holding the return address elsewhere.
Choose R33 for tidiness.

Acked-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-11-18 15:57:08 +10:00
Richard Henderson
6d264b38fc tcg-ia64: Simplify brcond
There was a misconception that a stop bit is required between a compare
and the branch that uses the predicate set by the compare.  This lead to
the usage of an extra bundle in which to perform the compare.  The extra
bundle left room for constants to be loaded for use with the compare insn.

If we pack the compare and the branch together in the same bundle, then
there's no longer any room for non-zero constants.  At which point we
can eliminate half the function by not handling them.

Acked-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-11-18 15:56:42 +10:00
Richard Henderson
6f65c780b9 tcg-ia64: Handle constant calls
Using only indirect calls results in 3 bundles (one to load the
descriptor address), and 4 stop bits.  By looking through the
descriptor to the constants, we can perform the call with 2
bundles and only 1 stop bit.

Acked-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-11-18 15:56:30 +10:00
Richard Henderson
5f7b16877a tcg-ia64: Use shortcuts for nop insns
There's no need to go through the full opcode-to-insn function call
to generate nops.  This makes the source a bit more readable.

Acked-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-11-18 15:56:25 +10:00
Richard Henderson
e3afa1c4ad tcg-ia64: Use TCGMemOp within qemu_ldst routines
Acked-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-11-18 15:56:12 +10:00
Richard Henderson
3cf246f0d4 tcg: Add tcg-be-null.h
This is a no-op backend data implementation, for those targets that
are not currently using the load/store optimization path.

This is prepatory to always requiring these functions in all backends.

Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-10 11:44:26 -07:00
Richard Henderson
e58eb53413 exec: Split softmmu_defs.h
The _cmmu helpers can be moved to exec-all.h.  The helpers that are
used from TCG will shortly need access to tcg_target_long so move
their declarations into tcg.h.

This requires minor include adjustments to all TCG backends.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-02 09:08:30 -07:00
Richard Henderson
a05b5b9be0 tcg: Change tcg_out_ld/st offset to intptr_t
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-02 09:08:30 -07:00
Richard Henderson
2ba7fae29e tcg: Change relocation offsets to intptr_t
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-02 09:08:29 -07:00
Paolo Bonzini
022c62cbbc exec: move include files to include/exec/
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-12-19 08:31:31 +01:00
Richard Henderson
c7d4475a70 tcg-ia64: Implement deposit
Note that in the general reg=reg,reg case we're restricted
to 16-bit insertions.  This makes it easy to allow "any"
constant as input, as post-truncation it will fit into the
constant load insn for which we have room in the bundle.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-17 01:26:43 +02:00
Aurelien Jarno
63975ea7df tcg/ia64: slightly optimize TLB access code
It is possible to slightly optimize the TLB access code, by replacing
the movi + and instructions by a deposit instruction.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-17 01:26:43 +02:00
Aurelien Jarno
2174d1e1ff tcg/ia64: remove suboptimal register shifting in qemu_ld/st ops
Remove suboptimal register shifting in qemu_ld/st ops, introduced at the
CONFIG_TCG_PASS_AREG0 time.

As mem_idx is now loaded in register R58/R59 for the slow path, we have
to make sure to do it last, to not add additional register constraints.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-17 01:26:43 +02:00
Aurelien Jarno
b90cf71692 tcg/ia64: implement movcond_i32/64
Implement movcond_i32/64 on ia64 hosts. It is not possible to have
immediate compare arguments without adding a new bundle, but it is
possible to have 22-bit immediate value arguments.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-17 01:26:42 +02:00
Blue Swirl
da897bf5ae tcg/ia64: use stack for TCG temps
Use stack instead of temp_buf array in CPUState for TCG temps.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-17 01:26:42 +02:00
Aurelien Jarno
626cd050e2 tcg: remove obsolete jmp op
The TCG jmp operation doesn't really make sense in the QEMU context, it
is unused, it is not implemented by some targets, and it is wrongly
implemented by some others.

This patch simply removes it.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Acked-by: Blue Swirl <blauwirbel@gmail.com>
Acked-by: Stefan Weil<sw@weilnetz.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-06 18:47:04 +02:00
Stefan Weil
6e17d0c5cd tcg: Remove tcg_target_get_call_iarg_regs_count
The TCG targets no longer need individual implementations.

Since commit 6a18ae2d29,
'flags' is no longer used in tcg_target_get_call_iarg_regs_count.

The remaining tcg_target_get_call_iarg_regs_count is trivial and only
called once. Therefore the patch eliminates it completely.

Signed-off-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-22 16:52:37 +02:00
Blue Swirl
89c33337fd Remove unused CONFIG_TCG_PASS_AREG0 and dead code
Now that CONFIG_TCG_PASS_AREG0 is enabled for all targets,
remove dead code and support for !CONFIG_TCG_PASS_AREG0 case.

Remove dyngen-exec.h and all references to it. Although included by
hw/spapr_hcall.c, it does not seem to use it.

Remove unused HELPER_CFLAGS.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2012-09-15 17:51:14 +00:00
Aurelien Jarno
d03c98d80f tcg/ia64: fix and optimize ld/st slow path
Store slow path has been broken in e141ab52d:
- the arguments are shifted before the last one (mem_index) is written.
- the shift is done for both slow and fast paths.

Fix that. Also optimize a bit by bundling the move together. This still
can be optimized, but it's better to wait for a decision to be taken on
the arguments order.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-08-26 21:10:37 +02:00
Aurelien Jarno
18d445b443 tcg/ia64: fix prologue/epilogue
Prologue and epilogue code has been broken in cea5f9a28.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-08-26 21:10:28 +02:00
Blue Swirl
e141ab52d2 softmmu templates: optionally pass CPUState to memory access functions
Optionally, make memory access helpers take a parameter for CPUState
instead of relying on global env.

On most targets, perform simple moves to reorder registers. On i386,
switch from regparm(3) calling convention to standard stack-based
version.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-03-18 12:21:52 +00:00
Andreas Färber
9349b4f9fd Rename CPUState -> CPUArchState
Scripted conversion:
  for file in *.[hc] hw/*.[hc] hw/kvm/*.[hc] linux-user/*.[hc] linux-user/m68k/*.[hc] bsd-user/*.[hc] darwin-user/*.[hc] tcg/*/*.[hc] target-*/cpu.h; do
    sed -i "s/CPUState/CPUArchState/g" $file
  done

All occurrences of CPUArchState are expected to be replaced by QOM CPUState,
once all targets are QOM'ified and common fields have been extracted.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
2012-03-14 22:20:27 +01:00
Richard Henderson
2a534aff30 tcg: Use TCGReg for standard tcg-target entry points.
Including tcg_out_ld, tcg_out_st, tcg_out_mov, tcg_out_movi.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-11-14 17:47:27 +01:00
Peter Maydell
498562926d tcg/ia64: Remove unused tcg_out_addi()
Remove the unused function tcg_out_addi() from the ia64 TCG backend;
this brings it into line with other backends.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-08 15:20:46 +00:00
Stefan Weil
af15a62309 tcg/ia64: Only one call output register needed for 64 bit hosts
The second register is never used for ia64 hosts.

Cc: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-17 17:54:57 +00:00
Richard Henderson
64ba39af27 tcg-ia64: Fix typos in AREG0 setup in prologue.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-08-21 18:52:26 +00:00
Blue Swirl
614f104dfd Delegate setup of TCG temporaries to targets
Delegate TCG temp_buf setup to targets, so that they can use a stack
frame later instead.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26 18:25:43 +00:00
Blue Swirl
cea5f9a28f cpu-exec.c: avoid AREG0 use
Make functions take a parameter for CPUState instead of relying
on global env. Pass CPUState pointer to TCG prologue, which moves
it to AREG0.

Thanks to Peter Maydell and Laurent Desnogues for the ARM prologue
change.

Revert the hacks to avoid AREG0 use on Sparc hosts.

Move cpu_has_work() and cpu_pc_from_tb() from exec.h to cpu.h.

Compile the file without HELPER_CFLAGS.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26 18:25:38 +00:00
Aurelien Jarno
5677903453 tcg arm/mips/ia64: add a comment about retranslation and caches
Add a comment about cache coherency and retranslation, so that people
developping new targets based on existing ones are warned of the issue.

Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-12 00:06:07 +01:00
Aurelien Jarno
a3e28aa5c7 tcg/ia64: remove an unnecessary stop bit
Spotted by Richard Henderson.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-10 01:39:49 +01:00
Richard Henderson
393f398b69 tcg-ia64: Fix warning in qemu_ld.
The usermode version of qemu_ld doesn't used mem_index,
leading to set-but-not-used warnings.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
2010-12-01 19:48:31 +01:00
Richard Henderson
07f59737d8 tcg-ia64: Fix address compilation in qemu_st.
A typo in the usermode address calculation path; R3 used where R2 needed.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
2010-12-01 19:48:31 +01:00
Richard Henderson
650a217a65 tcg-ia64: Fix tlb read error for 32-bit targets.
Use ld4 not ld8 for reading the tlb of 32-bit targets.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
2010-12-01 19:48:31 +01:00
Richard Henderson
b3b0091f07 tcg-ia64: Implement qemu_ld32.
The port was not properly merged following
86feb1c860

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
2010-12-01 19:48:31 +01:00
Richard Henderson
255108c0e3 tcg-ia64: Provide default GUEST_BASE.
Fix compilation error when GUEST_BASE is not defined.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
2010-12-01 19:48:31 +01:00
Richard Henderson
e4d58b41f9 tcg: Make some tcg-target.c routines static.
Both tcg_target_init and tcg_target_qemu_prologue
are unused outside of tcg.c.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09 11:18:26 +02:00
Richard Henderson
3b6dac3416 tcg: Add TYPE parameter to tcg_out_mov.
Mirror tcg_out_movi in having a TYPE parameter.  This allows x86_64
to perform the move at the proper width, which may elide a REX prefix.

Introduce a TCG_TYPE_REG enumerator to represent the "native width"
of the host register, and to distinguish the usage from "pointer data"
as represented by the existing TCG_TYPE_PTR.

Update all targets to match.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09 11:18:25 +02:00
Richard Henderson
6781d08d2e tcg-ia64: Load GUEST_BASE into a register.
Saves one bundle per memory operation.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-21 18:41:21 +02:00
Richard Henderson
7221f058a6 tcg-ia64: Fix some register usage issues.
(1) The output registers were not marked call-clobbered, even though
    they can be modified by called functions.
(2) The thread pointer was not marked reserved.
(3) R4-R6 are call-saved, but not saved by the prologue.  Rather than
    save them, mark them reserved so that we don't use them.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-21 18:41:21 +02:00
Aurelien Jarno
a175b996b2 tcg/ia64: fix tlb addend read
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-08 11:11:21 +02:00
Aurelien Jarno
477ba62001 tcg: initial ia64 support
A few words about design choices:
* On IA64, instructions should be grouped by bundle, and dependencies
  between instructions declared. A first version of this code tried to
  schedule instructions automatically, but was very complex and too
  invasive for the current common TCG code (ops not ending at
  instruction boundaries, code retranslation breaking already generated
  code, etc.)  It was also not very efficient, as dependencies between
  TCG ops is not available.
  Instead the option taken by the current implementation does not try
  to fill the bundle by scheduling instructions, but by providing ops
  not available as an ia64 instruction, and by offering 22-bit constant
  loading for most of the instructions. With both options the bundle are
  filled at approximately the same level.

* Up to 128 registers can be affected to a function on IA64, but TCG
  limits this number to 64, which is actually more than enough. The
  register affectation is the following:
  - r0: used to map a constant argument with value 0
  - r1: global pointer
  - r2, r3: internal use
  - r4 to r6: not used to avoid saving them
  - r7: env structure
  - r8 to r11: free for TCG (call clobbered)
  - r12: stack pointer
  - r13: thread pointer
  - r14 to r31: free for TCG (call clobbered)
  - r32: reserved (return address)
  - r33: reserved (PFS)
  - r33 to r63: free for TCG

* The IA64 architecture has only 64-bit registers and no 32-bit
  instructions (the only exception being cmp4). Therefore 64-bit
  registers and instructions are used for 32-bit ops. The adopted
  strategy is the same as the ABI, that is the higher 32 bits are
  undefined. Most ops (and, or, add, shl, etc.) can directly use
  the 64-bit registers, while some others have to sign-extend (sar,
  div, etc.) or zero-extend (shr, divu, etc.) the register first.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-01 21:51:59 +02:00