Clément Chigot 0fa5cd4a60 hw/intc/grlib_irqmp: implements multicore irq ... Now there is an ncpus property, use it in order to deliver the IRQ to multiple CPU. Co-developed-by: Frederic Konrad <konrad.frederic@yahoo.fr> Signed-off-by: Clément Chigot <chigot@adacore.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240131085047.18458-5-chigot@adacore.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>		2024-02-15 16:58:46 +01:00
..
allwinner-a10-pic.h
arm_gic_common.h
arm_gic.h
arm_gicv3_common.h
arm_gicv3_its_common.h
arm_gicv3.h
armv7m_nvic.h	hw/arm/armv7m: Make 'hw/intc/armv7m_nvic.h' a target agnostic header	2024-01-26 11:30:49 +00:00
aspeed_vic.h
bcm2835_ic.h
bcm2836_control.h
exynos4210_combiner.h
exynos4210_gic.h
goldfish_pic.h
grlib_irqmp.h	hw/intc/grlib_irqmp: implements multicore irq	2024-02-15 16:58:46 +01:00
heathrow_pic.h
i8259.h
imx_avic.h
imx_gpcv2.h
intc.h
ioapic.h
kvm_irqcount.h
loongarch_extioi.h	hw/intc/loongarch_extioi: Add dynamic cpu number support	2024-01-11 19:22:47 +08:00
loongarch_ipi.h
loongarch_pch_msi.h
loongarch_pch_pic.h
loongson_liointc.h
m68k_irqc.h
mips_gic.h
nios2_vic.h
ppc-uic.h
realview_gic.h
riscv_aclint.h
riscv_aplic.h
riscv_imsic.h
rx_icu.h
sifive_plic.h
xlnx-pmu-iomod-intc.h
xlnx-zynqmp-ipi.h