fa7ce0b028
Adjust the test-avx.py generator to produce tests specifically for MMX and 3DNow. Using a separate generator introduces some code duplication, but is a simpler approach because of test-avx's extra complexity to support 3- and 4-operand AVX instructions. If needed, a common library can be introduced later. While at it, for consistency move all the -cpu max rules to the same place. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
245 lines
6.1 KiB
Python
Executable File
245 lines
6.1 KiB
Python
Executable File
#! /usr/bin/env python3
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# Generate test-avx.h from x86.csv
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import csv
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import sys
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from fnmatch import fnmatch
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ignore = set(["EMMS", "FEMMS", "FISTTP",
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"LDMXCSR", "VLDMXCSR", "STMXCSR", "VSTMXCSR"])
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imask = {
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'PALIGNR': 0x3f,
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'PEXTRB': 0x0f,
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'PEXTRW': 0x07,
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'PEXTRD': 0x03,
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'PEXTRQ': 0x01,
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'PINSRB': 0x0f,
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'PINSRW': 0x07,
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'PINSRD': 0x03,
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'PINSRQ': 0x01,
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'PSHUF[DW]': 0xff,
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'PSHUF[LH]W': 0xff,
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'PS[LR][AL][WDQ]': 0x3f,
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}
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def strip_comments(x):
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for l in x:
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if l != '' and l[0] != '#':
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yield l
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def reg_w(w):
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if w == 8:
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return 'al'
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elif w == 16:
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return 'ax'
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elif w == 32:
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return 'eax'
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elif w == 64:
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return 'rax'
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raise Exception("bad reg_w %d" % w)
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def mem_w(w):
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if w == 8:
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t = "BYTE"
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elif w == 16:
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t = "WORD"
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elif w == 32:
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t = "DWORD"
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elif w == 64:
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t = "QWORD"
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else:
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raise Exception()
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return t + " PTR 32[rdx]"
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class MMArg():
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isxmm = True
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def __init__(self, mw):
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if mw not in [0, 32, 64]:
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raise Exception("Bad /m width: %s" % w)
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self.mw = mw
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self.ismem = mw != 0
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def regstr(self, n):
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if n < 0:
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return mem_w(self.mw)
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else:
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return "mm%d" % (n, )
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def match(op, pattern):
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return fnmatch(op, pattern)
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class ArgImm8u():
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isxmm = False
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ismem = False
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def __init__(self, op):
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for k, v in imask.items():
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if match(op, k):
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self.mask = imask[k];
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return
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raise Exception("Unknown immediate")
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def vals(self):
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mask = self.mask
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yield 0
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n = 0
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while n != mask:
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n += 1
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while (n & ~mask) != 0:
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n += (n & ~mask)
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yield n
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class ArgRM():
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isxmm = False
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def __init__(self, rw, mw):
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if rw not in [8, 16, 32, 64]:
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raise Exception("Bad r/w width: %s" % w)
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if mw not in [0, 8, 16, 32, 64]:
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raise Exception("Bad r/w width: %s" % w)
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self.rw = rw
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self.mw = mw
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self.ismem = mw != 0
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def regstr(self, n):
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if n < 0:
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return mem_w(self.mw)
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else:
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return reg_w(self.rw)
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class ArgMem():
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isxmm = False
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ismem = True
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def __init__(self, w):
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if w not in [8, 16, 32, 64, 128, 256]:
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raise Exception("Bad mem width: %s" % w)
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self.w = w
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def regstr(self, n):
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return mem_w(self.w)
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class SkipInstruction(Exception):
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pass
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def ArgGenerator(arg, op):
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if arg[:2] == 'mm':
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if "/" in arg:
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r, m = arg.split('/')
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if (m[0] != 'm'):
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raise Exception("Expected /m: %s", arg)
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return MMArg(int(m[1:]));
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else:
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return MMArg(0);
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elif arg[:4] == 'imm8':
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return ArgImm8u(op);
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elif arg[0] == 'r':
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if '/m' in arg:
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r, m = arg.split('/')
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if (m[0] != 'm'):
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raise Exception("Expected /m: %s", arg)
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mw = int(m[1:])
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if r == 'r':
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rw = mw
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else:
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rw = int(r[1:])
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return ArgRM(rw, mw)
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return ArgRM(int(arg[1:]), 0);
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elif arg[0] == 'm':
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return ArgMem(int(arg[1:]))
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else:
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raise SkipInstruction
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class InsnGenerator:
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def __init__(self, op, args):
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self.op = op
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if op[0:2] == "PF":
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self.optype = 'F32'
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else:
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self.optype = 'I'
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try:
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self.args = list(ArgGenerator(a, op) for a in args)
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if len(self.args) > 0 and self.args[-1] is None:
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self.args = self.args[:-1]
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except SkipInstruction:
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raise
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except Exception as e:
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raise Exception("Bad arg %s: %s" % (op, e))
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def gen(self):
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regs = (5, 6, 7)
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dest = 4
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nreg = len(self.args)
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if nreg == 0:
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yield self.op
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return
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if isinstance(self.args[-1], ArgImm8u):
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nreg -= 1
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immarg = self.args[-1]
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else:
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immarg = None
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memarg = -1
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for n, arg in enumerate(self.args):
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if arg.ismem:
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memarg = n
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if nreg == 1:
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regset = [(regs[0],)]
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if memarg == 0:
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regset += [(-1,)]
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elif nreg == 2:
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regset = [
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(regs[0], regs[1]),
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(regs[0], regs[0]),
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]
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if memarg == 0:
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regset += [(-1, regs[0])]
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elif memarg == 1:
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regset += [(dest, -1)]
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else:
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raise Exception("Too many regs: %s(%d)" % (self.op, nreg))
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for regv in regset:
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argstr = []
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for i in range(nreg):
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arg = self.args[i]
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argstr.append(arg.regstr(regv[i]))
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if immarg is None:
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yield self.op + ' ' + ','.join(argstr)
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else:
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for immval in immarg.vals():
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yield self.op + ' ' + ','.join(argstr) + ',' + str(immval)
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def split0(s):
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if s == '':
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return []
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return s.split(',')
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def main():
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n = 0
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if len(sys.argv) <= 3:
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print("Usage: test-mmx.py x86.csv test-mmx.h CPUID...")
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exit(1)
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csvfile = open(sys.argv[1], 'r', newline='')
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archs = sys.argv[3:]
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with open(sys.argv[2], "w") as outf:
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outf.write("// Generated by test-mmx.py. Do not edit.\n")
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for row in csv.reader(strip_comments(csvfile)):
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insn = row[0].replace(',', '').split()
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if insn[0] in ignore:
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continue
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cpuid = row[6]
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if cpuid in archs:
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try:
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g = InsnGenerator(insn[0], insn[1:])
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for insn in g.gen():
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outf.write('TEST(%d, "%s", %s)\n' % (n, insn, g.optype))
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n += 1
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except SkipInstruction:
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pass
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outf.write("#undef TEST\n")
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csvfile.close()
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if __name__ == "__main__":
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main()
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