d18b065286
The patch below fixes a bug in the VSX_CVT_FP_TO_INT and VSX_CVT_FP_TO_INT2 macros in target/ppc/fpu_helper.c where a non-NaN floating point value from the source vector is incorrectly converted to 0, 0x80000000, or 0x8000000000000000 instead of the expected value if a preceding source floating point value from the same source vector was a NaN. The bug in the VSX_CVT_FP_TO_INT and VSX_CVT_FP_TO_INT2 macros in target/ppc/fpu_helper.c was introduced with commitc3f24257e3. This patch also adds a new vsx_f2i_nan test in tests/tcg/ppc64 that checks that the VSX xvcvspsxws, xvcvspuxws, xvcvspsxds, xvcvspuxds, xvcvdpsxws, xvcvdpuxws, xvcvdpsxds, and xvcvdpuxds instructions correctly convert non-NaN floating point values to integer values if the source vector contains NaN floating point values. Fixes:c3f24257e3("target/ppc: Clear fpstatus flags on helpers missing it") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1941 Signed-off-by: John Platts <john_platts@hotmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
301 lines
12 KiB
C
301 lines
12 KiB
C
#include <stdio.h>
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#include "qemu/compiler.h"
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typedef vector float vsx_float32_vec_t;
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typedef vector double vsx_float64_vec_t;
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typedef vector signed int vsx_int32_vec_t;
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typedef vector unsigned int vsx_uint32_vec_t;
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typedef vector signed long long vsx_int64_vec_t;
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typedef vector unsigned long long vsx_uint64_vec_t;
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#define DEFINE_VSX_F2I_FUNC(SRC_T, DEST_T, INSN) \
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static inline vsx_##DEST_T##_vec_t \
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vsx_convert_##SRC_T##_vec_to_##DEST_T##_vec(vsx_##SRC_T##_vec_t v) \
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{ \
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vsx_##DEST_T##_vec_t result; \
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asm(#INSN " %x0, %x1" : "=wa" (result) : "wa" (v)); \
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return result; \
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}
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DEFINE_VSX_F2I_FUNC(float32, int32, xvcvspsxws)
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DEFINE_VSX_F2I_FUNC(float32, uint32, xvcvspuxws)
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DEFINE_VSX_F2I_FUNC(float32, int64, xvcvspsxds)
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DEFINE_VSX_F2I_FUNC(float32, uint64, xvcvspuxds)
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DEFINE_VSX_F2I_FUNC(float64, int32, xvcvdpsxws)
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DEFINE_VSX_F2I_FUNC(float64, uint32, xvcvdpuxws)
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DEFINE_VSX_F2I_FUNC(float64, int64, xvcvdpsxds)
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DEFINE_VSX_F2I_FUNC(float64, uint64, xvcvdpuxds)
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static inline vsx_float32_vec_t vsx_float32_is_nan(vsx_float32_vec_t v)
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{
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vsx_float32_vec_t abs_v;
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vsx_float32_vec_t result_mask;
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const vsx_uint32_vec_t f32_pos_inf_bits = {0x7F800000U, 0x7F800000U,
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0x7F800000U, 0x7F800000U};
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asm("xvabssp %x0, %x1" : "=wa" (abs_v) : "wa" (v));
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asm("vcmpgtuw %0, %1, %2"
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: "=v" (result_mask)
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: "v" (abs_v), "v" (f32_pos_inf_bits));
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return result_mask;
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}
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static inline vsx_float64_vec_t vsx_float64_is_nan(vsx_float64_vec_t v)
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{
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vsx_float64_vec_t abs_v;
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vsx_float64_vec_t result_mask;
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const vsx_uint64_vec_t f64_pos_inf_bits = {0x7FF0000000000000ULL,
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0x7FF0000000000000ULL};
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asm("xvabsdp %x0, %x1" : "=wa" (abs_v) : "wa" (v));
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asm("vcmpgtud %0, %1, %2"
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: "=v" (result_mask)
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: "v" (abs_v), "v" (f64_pos_inf_bits));
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return result_mask;
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}
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#define DEFINE_VSX_BINARY_LOGICAL_OP_INSN(LANE_TYPE, OP_NAME, OP_INSN) \
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static inline vsx_##LANE_TYPE##_vec_t vsx_##LANE_TYPE##_##OP_NAME( \
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vsx_##LANE_TYPE##_vec_t a, vsx_##LANE_TYPE##_vec_t b) \
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{ \
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vsx_##LANE_TYPE##_vec_t result; \
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asm(#OP_INSN " %x0, %x1, %x2" : "=wa" (result) : "wa" (a), "wa" (b)); \
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return result; \
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}
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DEFINE_VSX_BINARY_LOGICAL_OP_INSN(float32, logical_and, xxland)
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DEFINE_VSX_BINARY_LOGICAL_OP_INSN(float64, logical_and, xxland)
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DEFINE_VSX_BINARY_LOGICAL_OP_INSN(int32, logical_and, xxland)
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DEFINE_VSX_BINARY_LOGICAL_OP_INSN(uint32, logical_and, xxland)
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DEFINE_VSX_BINARY_LOGICAL_OP_INSN(int64, logical_and, xxland)
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DEFINE_VSX_BINARY_LOGICAL_OP_INSN(uint64, logical_and, xxland)
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DEFINE_VSX_BINARY_LOGICAL_OP_INSN(float32, logical_andc, xxlandc)
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DEFINE_VSX_BINARY_LOGICAL_OP_INSN(float64, logical_andc, xxlandc)
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DEFINE_VSX_BINARY_LOGICAL_OP_INSN(float32, logical_or, xxlor)
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DEFINE_VSX_BINARY_LOGICAL_OP_INSN(float64, logical_or, xxlor)
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DEFINE_VSX_BINARY_LOGICAL_OP_INSN(int32, logical_or, xxlor)
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DEFINE_VSX_BINARY_LOGICAL_OP_INSN(uint32, logical_or, xxlor)
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DEFINE_VSX_BINARY_LOGICAL_OP_INSN(int64, logical_or, xxlor)
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DEFINE_VSX_BINARY_LOGICAL_OP_INSN(uint64, logical_or, xxlor)
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static inline vsx_int32_vec_t vsx_mask_out_float32_vec_to_int32_vec(
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vsx_int32_vec_t v)
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{
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return v;
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}
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static inline vsx_uint32_vec_t vsx_mask_out_float32_vec_to_uint32_vec(
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vsx_uint32_vec_t v)
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{
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return v;
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}
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static inline vsx_int64_vec_t vsx_mask_out_float32_vec_to_int64_vec(
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vsx_int64_vec_t v)
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{
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return v;
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}
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static inline vsx_uint64_vec_t vsx_mask_out_float32_vec_to_uint64_vec(
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vsx_uint64_vec_t v)
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{
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return v;
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}
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static inline vsx_int32_vec_t vsx_mask_out_float64_vec_to_int32_vec(
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vsx_int32_vec_t v)
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{
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#if HOST_BIG_ENDIAN
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const vsx_int32_vec_t valid_lanes_mask = {-1, 0, -1, 0};
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#else
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const vsx_int32_vec_t valid_lanes_mask = {0, -1, 0, -1};
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#endif
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return vsx_int32_logical_and(v, valid_lanes_mask);
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}
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static inline vsx_uint32_vec_t vsx_mask_out_float64_vec_to_uint32_vec(
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vsx_uint32_vec_t v)
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{
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return (vsx_uint32_vec_t)vsx_mask_out_float64_vec_to_int32_vec(
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(vsx_int32_vec_t)v);
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}
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static inline vsx_int64_vec_t vsx_mask_out_float64_vec_to_int64_vec(
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vsx_int64_vec_t v)
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{
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return v;
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}
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static inline vsx_uint64_vec_t vsx_mask_out_float64_vec_to_uint64_vec(
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vsx_uint64_vec_t v)
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{
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return v;
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}
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static inline void print_vsx_float32_vec_elements(FILE *stream,
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vsx_float32_vec_t vec)
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{
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fprintf(stream, "%g, %g, %g, %g", (double)vec[0], (double)vec[1],
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(double)vec[2], (double)vec[3]);
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}
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static inline void print_vsx_float64_vec_elements(FILE *stream,
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vsx_float64_vec_t vec)
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{
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fprintf(stream, "%.17g, %.17g", vec[0], vec[1]);
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}
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static inline void print_vsx_int32_vec_elements(FILE *stream,
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vsx_int32_vec_t vec)
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{
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fprintf(stream, "%d, %d, %d, %d", vec[0], vec[1], vec[2], vec[3]);
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}
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static inline void print_vsx_uint32_vec_elements(FILE *stream,
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vsx_uint32_vec_t vec)
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{
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fprintf(stream, "%u, %u, %u, %u", vec[0], vec[1], vec[2], vec[3]);
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}
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static inline void print_vsx_int64_vec_elements(FILE *stream,
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vsx_int64_vec_t vec)
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{
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fprintf(stream, "%lld, %lld", vec[0], vec[1]);
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}
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static inline void print_vsx_uint64_vec_elements(FILE *stream,
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vsx_uint64_vec_t vec)
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{
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fprintf(stream, "%llu, %llu", vec[0], vec[1]);
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}
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#define DEFINE_VSX_ALL_EQ_FUNC(LANE_TYPE, CMP_INSN) \
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static inline int vsx_##LANE_TYPE##_all_eq(vsx_##LANE_TYPE##_vec_t a, \
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vsx_##LANE_TYPE##_vec_t b) \
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{ \
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unsigned result; \
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vsx_##LANE_TYPE##_vec_t is_eq_mask_vec; \
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asm(#CMP_INSN ". %0, %2, %3\n\t" \
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"mfocrf %1, 2" \
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: "=v" (is_eq_mask_vec), "=r" (result) \
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: "v" (a), "v" (b) \
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: "cr6"); \
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return (int)((result >> 7) & 1u); \
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}
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DEFINE_VSX_ALL_EQ_FUNC(int32, vcmpequw)
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DEFINE_VSX_ALL_EQ_FUNC(uint32, vcmpequw)
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DEFINE_VSX_ALL_EQ_FUNC(int64, vcmpequd)
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DEFINE_VSX_ALL_EQ_FUNC(uint64, vcmpequd)
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#define DEFINE_VSX_F2I_TEST_FUNC(SRC_T, DEST_T) \
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static inline int test_vsx_conv_##SRC_T##_vec_to_##DEST_T##_vec( \
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vsx_##SRC_T##_vec_t src_v) \
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{ \
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const vsx_##SRC_T##_vec_t is_nan_mask = vsx_##SRC_T##_is_nan(src_v); \
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const vsx_##SRC_T##_vec_t nan_src_v = \
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vsx_##SRC_T##_logical_and(src_v, is_nan_mask); \
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const vsx_##SRC_T##_vec_t non_nan_src_v = \
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vsx_##SRC_T##_logical_andc(src_v, is_nan_mask); \
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\
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const vsx_##DEST_T##_vec_t expected_result = \
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vsx_mask_out_##SRC_T##_vec_to_##DEST_T##_vec( \
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vsx_##DEST_T##_logical_or( \
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vsx_convert_##SRC_T##_vec_to_##DEST_T##_vec(nan_src_v), \
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vsx_convert_##SRC_T##_vec_to_##DEST_T##_vec( \
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non_nan_src_v))); \
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const vsx_##DEST_T##_vec_t actual_result = \
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vsx_mask_out_##SRC_T##_vec_to_##DEST_T##_vec( \
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vsx_convert_##SRC_T##_vec_to_##DEST_T##_vec(src_v)); \
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const int test_result = \
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vsx_##DEST_T##_all_eq(expected_result, actual_result); \
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\
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if (unlikely(test_result == 0)) { \
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fputs("FAIL: Conversion of " #SRC_T " vector to " #DEST_T \
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" vector failed\n", stdout); \
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fputs("Source values: ", stdout); \
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print_vsx_##SRC_T##_vec_elements(stdout, src_v); \
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fputs("\nExpected result: ", stdout); \
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print_vsx_##DEST_T##_vec_elements(stdout, expected_result); \
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fputs("\nActual result: ", stdout); \
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print_vsx_##DEST_T##_vec_elements(stdout, actual_result); \
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fputs("\n\n", stdout); \
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} \
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\
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return test_result; \
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}
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DEFINE_VSX_F2I_TEST_FUNC(float32, int32)
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DEFINE_VSX_F2I_TEST_FUNC(float32, uint32)
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DEFINE_VSX_F2I_TEST_FUNC(float32, int64)
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DEFINE_VSX_F2I_TEST_FUNC(float32, uint64)
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DEFINE_VSX_F2I_TEST_FUNC(float64, int32)
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DEFINE_VSX_F2I_TEST_FUNC(float64, uint32)
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DEFINE_VSX_F2I_TEST_FUNC(float64, int64)
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DEFINE_VSX_F2I_TEST_FUNC(float64, uint64)
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static inline vsx_int32_vec_t vsx_int32_vec_from_mask(int mask)
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{
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const vsx_int32_vec_t bits_to_test = {1, 2, 4, 8};
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const vsx_int32_vec_t vec_mask = {mask, mask, mask, mask};
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vsx_int32_vec_t result;
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asm("vcmpequw %0, %1, %2"
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: "=v" (result)
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: "v" (vsx_int32_logical_and(vec_mask, bits_to_test)),
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"v" (bits_to_test));
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return result;
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}
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static inline vsx_int64_vec_t vsx_int64_vec_from_mask(int mask)
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{
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const vsx_int64_vec_t bits_to_test = {1, 2};
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const vsx_int64_vec_t vec_mask = {mask, mask};
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vsx_int64_vec_t result;
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asm("vcmpequd %0, %1, %2"
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: "=v" (result)
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: "v" (vsx_int64_logical_and(vec_mask, bits_to_test)),
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"v" (bits_to_test));
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return result;
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}
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int main(void)
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{
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const vsx_float32_vec_t f32_iota1 = {1.0f, 2.0f, 3.0f, 4.0f};
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const vsx_float64_vec_t f64_iota1 = {1.0, 2.0};
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int num_of_tests_failed = 0;
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for (int i = 0; i < 16; i++) {
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const vsx_int32_vec_t nan_mask = vsx_int32_vec_from_mask(i);
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const vsx_float32_vec_t f32_v =
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vsx_float32_logical_or(f32_iota1, (vsx_float32_vec_t)nan_mask);
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num_of_tests_failed +=
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(int)(!test_vsx_conv_float32_vec_to_int32_vec(f32_v));
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num_of_tests_failed +=
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(int)(!test_vsx_conv_float32_vec_to_int64_vec(f32_v));
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num_of_tests_failed +=
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(int)(!test_vsx_conv_float32_vec_to_uint32_vec(f32_v));
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num_of_tests_failed +=
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(int)(!test_vsx_conv_float32_vec_to_uint64_vec(f32_v));
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}
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for (int i = 0; i < 4; i++) {
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const vsx_int64_vec_t nan_mask = vsx_int64_vec_from_mask(i);
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const vsx_float64_vec_t f64_v =
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vsx_float64_logical_or(f64_iota1, (vsx_float64_vec_t)nan_mask);
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num_of_tests_failed +=
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(int)(!test_vsx_conv_float64_vec_to_int32_vec(f64_v));
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num_of_tests_failed +=
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(int)(!test_vsx_conv_float64_vec_to_int64_vec(f64_v));
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num_of_tests_failed +=
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(int)(!test_vsx_conv_float64_vec_to_uint32_vec(f64_v));
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num_of_tests_failed +=
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(int)(!test_vsx_conv_float64_vec_to_uint64_vec(f64_v));
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}
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printf("%d tests failed\n", num_of_tests_failed);
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return (int)(num_of_tests_failed != 0);
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}
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