qemu-e2k/target-lm32
Andreas Färber a47dddd734 exec: Change cpu_abort() argument to CPUState
Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13 19:52:28 +01:00
..
cpu-qom.h target-lm32: move model features to LM32CPU 2014-02-04 19:34:30 +01:00
cpu.c cpu: Move breakpoints field from CPU_COMMON to CPUState 2014-03-13 19:20:47 +01:00
cpu.h cpu: Move breakpoints field from CPU_COMMON to CPUState 2014-03-13 19:20:47 +01:00
gdbstub.c cpu: Introduce CPUClass::gdb_{read,write}_register() 2013-07-27 00:04:17 +02:00
helper.c exec: Change cpu_abort() argument to CPUState 2014-03-13 19:52:28 +01:00
helper.h target-lm32: stop VM on illegal or unknown instruction 2014-02-04 19:47:39 +01:00
machine.c
Makefile.objs cpu: Introduce CPUClass::gdb_{read,write}_register() 2013-07-27 00:04:17 +02:00
op_helper.c translate-all: Change cpu_restore_state() argument to CPUState 2014-03-13 19:20:47 +01:00
README
TODO target-lm32: add breakpoint/watchpoint support 2014-02-04 19:47:06 +01:00
translate.c cpu: Move breakpoints field from CPU_COMMON to CPUState 2014-03-13 19:20:47 +01:00

LatticeMico32 target
--------------------

General
-------
All opcodes including the JUART CSRs are supported.


JTAG UART
---------
JTAG UART is routed to a serial console device. For the current boards it
is the second one. Ie to enable it in the qemu virtual console window use
the following command line parameters:
  -serial vc -serial vc
This will make serial0 (the lm32_uart) and serial1 (the JTAG UART)
available as virtual consoles.


Programmatically terminate the emulator
----------------------------------------
Originally neither the LatticeMico32 nor its peripherals support a
mechanism to shut down the machine. Emulation aware programs can write to a
to a special register within the system control block to shut down the
virtual machine.  For more details see hw/lm32_sys.c. The lm32-evr is the
first BSP which instantiate this model. A (32 bit) write to 0xfff0000
causes a vm shutdown.


Special instructions
--------------------
The translation recognizes one special instruction to halt the cpu:
  and r0, r0, r0
On real hardware this instruction is a nop. It is not used by GCC and
should (hopefully) not be used within hand-crafted assembly.
Insert this instruction in your idle loop to reduce the cpu load on the
host.


Ignoring the MSB of the address bus
-----------------------------------
Some SoC ignores the MSB on the address bus. Thus creating a shadow memory
area. As a general rule, 0x00000000-0x7fffffff is cached, whereas
0x80000000-0xffffffff is not cached and used to access IO devices. This
behaviour can be enabled with:
  cpu_lm32_set_phys_msb_ignore(env, 1);