qemu-e2k/hw/dma
Francisco Iglesias 00f05c02f9 hw/dma/xlnx_csu_dma: Support starting a read transfer through a class method
An option on real hardware when embedding a DMA engine into a peripheral
is to make the peripheral control the engine through a custom DMA control
(hardware) interface between the two. Software drivers in this scenario
configure and trigger DMA operations through the controlling peripheral's
register API (for example, writing a specific bit in a register could
propagate down to a transfer start signal on the DMA control interface).
At the same time the status, results and interrupts for the transfer might
still be intended to be read and caught through the DMA engine's register
API (and signals).

This patch adds a class 'read' method for allowing to start read transfers
from peripherals embedding and controlling the Xilinx CSU DMA engine as in
above scenario.

Signed-off-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Message-id: 20220121161141.14389-6-francisco.iglesias@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-01-28 14:29:46 +00:00
..
bcm2835_dma.c
etraxfs_dma.c
i8257.c
i82374.c Use OBJECT_DECLARE_SIMPLE_TYPE when possible 2020-09-18 14:12:32 -04:00
Kconfig hw/dma: Implement a Xilinx CSU DMA model 2021-03-08 17:20:04 +00:00
meson.build Drop the deprecated unicore32 target 2021-05-12 18:20:52 +02:00
omap_dma.c
pl080.c Do not include exec/address-spaces.h if it's not really necessary 2021-05-02 17:24:51 +02:00
pl330.c dma: Let dma_memory_read/write() take MemTxAttrs argument 2021-12-30 17:16:32 +01:00
pxa2xx_dma.c hw/arm: Constify VMStateDescription 2021-05-02 17:24:50 +02:00
rc4030.c Use OBJECT_DECLARE_SIMPLE_TYPE when possible 2020-09-18 14:12:32 -04:00
sifive_pdma.c hw/dma: sifive_pdma: permit 4/8-byte access size of PDMA registers 2022-01-08 15:46:09 +10:00
soc_dma.c
sparc32_dma.c dma: Let dma_memory_read/write() take MemTxAttrs argument 2021-12-30 17:16:32 +01:00
trace-events docs: fix references to docs/devel/tracing.rst 2021-06-02 06:51:09 +02:00
trace.h
xilinx_axidma.c hw/dma/xilinx_axidma: Rename StreamSlave as StreamSink 2020-12-10 12:15:04 -05:00
xlnx_csu_dma.c hw/dma/xlnx_csu_dma: Support starting a read transfer through a class method 2022-01-28 14:29:46 +00:00
xlnx_dpdma.c dma: Let dma_memory_read/write() take MemTxAttrs argument 2021-12-30 17:16:32 +01:00
xlnx-zdma.c hw/dma/xlnx-zdma Always expect 'dma' link property to be set 2021-08-26 17:01:59 +01:00
xlnx-zynq-devcfg.c dma: Let dma_memory_read/write() take MemTxAttrs argument 2021-12-30 17:16:32 +01:00