Dylan Jhong 01e723bf18 target/riscv: Align the data type of reset vector address ... Use target_ulong to instead of uint64_t on reset vector address to adapt on both 32/64 machine. Signed-off-by: Dylan Jhong <dylan@andestech.com> Signed-off-by: Ruinland ChuanTzu Tsai <ruinland@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210329034801.22667-1-dylan@andestech.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2021-05-11 20:01:10 +10:00
..
insn_trans	riscv: Add semihosting support	2021-01-18 10:05:06 +00:00
arch_dump.c	target-riscv: support QMP dump-guest-memory	2021-03-04 09:43:29 -05:00
cpu_bits.h	target/riscv: Remove privilege v1.9 specific CSR related code	2021-05-11 20:01:10 +10:00
cpu_helper.c	target/riscv: Remove privilege v1.9 specific CSR related code	2021-05-11 20:01:10 +10:00
cpu_user.h
cpu-param.h	target/riscv: Add a virtualised MMU Mode	2020-11-09 15:08:45 -08:00
cpu.c	target/riscv: Align the data type of reset vector address	2021-05-11 20:01:10 +10:00
cpu.h	target/riscv: Remove privilege v1.9 specific CSR related code	2021-05-11 20:01:10 +10:00
csr.c	target/riscv: Remove privilege v1.9 specific CSR related code	2021-05-11 20:01:10 +10:00
fpu_helper.c	target/riscv: fpu_helper: Match function defs in HELPER macros	2020-12-17 21:56:44 -08:00
gdbstub.c	target/riscv: Generate the GDB XML file for CSR registers dynamically	2021-01-16 10:57:21 -08:00
helper.h	target/riscv: fpu_helper: Match function defs in HELPER macros	2020-12-17 21:56:44 -08:00
insn16-32.decode
insn16-64.decode
insn16.decode
insn32-64.decode
insn32.decode
instmap.h
internals.h	target/riscv: Add basic vmstate description of CPU	2020-11-03 07:17:23 -08:00
machine.c	target/riscv: Remove privilege v1.9 specific CSR related code	2021-05-11 20:01:10 +10:00
meson.build	target-riscv: support QMP dump-guest-memory	2021-03-04 09:43:29 -05:00
monitor.c	hmp: Pass monitor to mon_get_cpu_env()	2020-11-13 12:45:51 +00:00
op_helper.c	hw: Do not include qemu/log.h if it is not necessary	2021-05-02 17:24:50 +02:00
pmp.c	target/riscv: flush TLB pages if PMP permission has been changed	2021-03-22 21:54:40 -04:00
pmp.h	target/riscv: propagate PMP permission to TLB page	2021-03-22 21:54:40 -04:00
trace-events	trace-events: Fix attribution of trace points to source	2020-09-09 17:17:58 +01:00
trace.h
translate.c	target/riscv: Remove privilege v1.9 specific CSR related code	2021-05-11 20:01:10 +10:00
vector_helper.c