Aleksandar Markovic 03f400883a target/mips: Add MXU decoding engine ... Add MXU decoding engine: add handlers for all instruction pools, and main decode handler. The handlers, for now, for the purpose of this patch, contain only sceleton in the form of a single switch statement. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>		2018-10-29 14:13:47 +01:00
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alpha	target/alpha: remove tlb_flush from alpha_cpu_initfn	2018-10-18 18:58:10 -07:00
arm	target/arm: Only flush tlb if ASID changes	2018-10-24 07:51:37 +01:00
cris	target/cris/translate: Get rid of qemu_log_separate()	2018-10-16 17:57:23 +02:00
hppa	target/hppa: Raise exception 26 on emulated hardware	2018-10-16 15:32:22 -07:00
i386	Error reporting patches for 2018-10-22	2018-10-23 17:20:23 +01:00
lm32
m68k
microblaze	target-microblaze: Rework NOP/zero instruction handling	2018-06-15 09:05:00 +02:00
mips	target/mips: Add MXU decoding engine	2018-10-29 14:13:47 +01:00
moxie
nios2
openrisc	target/openrisc: Fix writes to interrupt mask register	2018-07-03 22:40:33 +09:00
ppc	Error reporting patches for 2018-10-22	2018-10-23 17:20:23 +01:00
riscv	RISC-V: Update CSR and interrupt definitions	2018-10-17 13:02:19 -07:00
s390x	target/s390x: Check HAVE_ATOMIC128 and HAVE_CMPXCHG128 at translate	2018-10-18 19:46:53 -07:00
sh4	sh4: fix use_icount with linux-user	2018-08-20 00:11:06 +02:00
sparc	SPARC64: add icount support	2018-06-17 11:13:06 +01:00
tilegx
tricore
unicore32	target/unicore32: remove tlb_flush from uc32_init_fn	2018-10-18 18:58:10 -07:00
xtensa	target/xtensa: extract gen_check_interrupts call	2018-10-01 11:08:36 -07:00