Richard Henderson 0e6bac3edb target/ppc: Remove MSR_SA and MSR_AP from hflags ... Nothing within the translator -- or anywhere else for that matter -- checks MSR_SA or MSR_AP on the 602. This may be a mistake. However, for the moment, we need not record these bits in hflags. This allows us to simplify HFLAGS_VSX computation by moving it to overlap with MSR_VSX. Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210323184340.619757-8-richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>		2021-05-04 11:41:24 +10:00
..
alpha	target/alpha: fix icount handling for timer instructions	2021-04-05 07:32:56 -07:00
arm	target/arm: Enforce alignment for sve LD1R	2021-04-30 11:16:51 +01:00
avr	target/avr: Fix interrupt execution	2021-03-15 00:39:52 +01:00
cris
hexagon	Hexagon (target/hexagon) CABAC decode bin	2021-05-01 16:06:11 -07:00
hppa
i386	i386: Add missing cpu feature bits in EPYC-Rome model	2021-04-09 16:02:18 -04:00
lm32
m68k
microblaze
mips	target/mips/rel6_translate: Change license to GNU LGPL v2.1 (or later)	2021-04-20 12:52:04 +01:00
moxie
nios2
openrisc	target/openrisc: fix icount handling for timer instructions	2021-04-01 10:37:20 +02:00
ppc	target/ppc: Remove MSR_SA and MSR_AP from hflags	2021-05-04 11:41:24 +10:00
riscv	target/riscv: Prevent lost illegal instruction exceptions	2021-03-22 21:54:40 -04:00
rx
s390x	target/s390x: fix s390_probe_access to check PAGE_WRITE_ORG for writeability	2021-04-23 14:10:56 +01:00
sh4
sparc
tricore	target/tricore: Fix OPC2_32_RRPW_EXTR for width=0	2021-03-14 14:49:01 +01:00
unicore32
xtensa	target/xtensa: make xtensa_modules static on import	2021-04-03 08:52:18 -07:00
meson.build