David Hildenbrand 13054739b5 s390x/tcg: store in the TB flags if AFP is enabled ... We exit the TB when changing the control registers, so just like PSW bits, this should always be consistent for a TB. Using the PSW bit semantic makes things a lot easier compared to manually defining the spare, shifted bits. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-4-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>		2018-10-04 10:32:39 +02:00
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alpha	…
arm	target/arm: Start AArch32 CPUs with EL2 but not EL3 in Hyp mode	2018-09-25 15:13:24 +01:00
cris	…
hppa	…
i386	target/i386: fix translation for icount mode	2018-10-02 19:09:13 +02:00
lm32	…
m68k	…
microblaze	…
mips	target/mips: Add definition of nanoMIPS I7200 CPU	2018-08-24 17:51:59 +02:00
moxie	…
nios2	…
openrisc	target/openrisc: Fix writes to interrupt mask register	2018-07-03 22:40:33 +09:00
ppc	target/ppc/cpu-models: Re-group the 970 CPUs together again	2018-09-25 11:12:25 +10:00
riscv	riscv: remove define cpu_init()	2018-09-05 09:58:38 -07:00
s390x	s390x/tcg: store in the TB flags if AFP is enabled	2018-10-04 10:32:39 +02:00
sh4	sh4: fix use_icount with linux-user	2018-08-20 00:11:06 +02:00
sparc	…
tilegx	…
tricore	…
unicore32	…
xtensa	target/xtensa: extract gen_check_interrupts call	2018-10-01 11:08:36 -07:00