qemu-e2k/include/hw/riscv
Anup Patel 18df0b4695 hw/riscv: virt: Allow creating multiple NUMA sockets
We extend RISC-V virt machine to allow creating a multi-socket
machine. Each RISC-V virt machine socket is a NUMA node having
a set of HARTs, a memory instance, a CLINT instance, and a PLIC
instance. Other devices are shared between all sockets. We also
update the generated device tree accordingly.

By default, NUMA multi-socket support is disabled for RISC-V virt
machine. To enable it, users can use "-numa" command-line options
of QEMU.

Example1: For two NUMA nodes with 2 CPUs each, append following
to command-line options: "-smp 4 -numa node -numa node"

Example2: For two NUMA nodes with 1 and 3 CPUs, append following
to command-line options:
"-smp 4 -numa node -numa node -numa cpu,node-id=0,core-id=0 \
-numa cpu,node-id=1,core-id=1 -numa cpu,node-id=1,core-id=2 \
-numa cpu,node-id=1,core-id=3"

The maximum number of sockets in a RISC-V virt machine is 8
but this limit can be changed in future.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Message-Id: <20200616032229.766089-6-anup.patel@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-08-25 09:11:35 -07:00
..
boot_opensbi.h riscv: Add opensbi firmware dynamic support 2020-07-13 17:25:37 -07:00
boot.h riscv: Add opensbi firmware dynamic support 2020-07-13 17:25:37 -07:00
numa.h hw/riscv: Add helpers for RISC-V multi-socket NUMA machines 2020-08-25 09:11:35 -07:00
opentitan.h riscv/opentitan: Connect the UART device 2020-06-19 08:24:07 -07:00
riscv_hart.h riscv: hart: Add a "hartid-base" property to RISC-V hart array 2019-09-17 08:42:47 -07:00
riscv_htif.h Clean up inclusion of sysemu/sysemu.h 2019-08-16 13:31:53 +02:00
sifive_clint.h hw/riscv: Allow creating multiple instances of CLINT 2020-08-25 09:11:35 -07:00
sifive_cpu.h riscv: Add a sifive_cpu.h to include both E and U cpu type defines 2019-09-17 08:42:46 -07:00
sifive_e_prci.h riscv: sifive_e: prci: Update the PRCI register block size 2019-09-17 08:42:46 -07:00
sifive_e.h sifive_e: Support the revB machine 2020-06-19 08:24:07 -07:00
sifive_gpio.h hw/riscv: sifive_gpio: Add a new 'ngpio' property 2020-06-19 08:24:07 -07:00
sifive_plic.h hw/riscv: Allow creating multiple instances of PLIC 2020-08-25 09:11:35 -07:00
sifive_test.h riscv: sifive_test: Add reset functionality 2019-09-17 08:42:44 -07:00
sifive_u_otp.h riscv: sifive: Implement a model for SiFive FU540 OTP 2019-09-17 08:42:49 -07:00
sifive_u_prci.h riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes 2019-09-17 08:42:48 -07:00
sifive_u.h hw/riscv: sifive_u: Add a dummy L2 cache controller device 2020-08-21 22:37:55 -07:00
sifive_uart.h include: Make headers more self-contained 2019-08-16 13:31:51 +02:00
spike.h hw/riscv: spike: Allow creating multiple NUMA sockets 2020-08-25 09:11:35 -07:00
virt.h hw/riscv: virt: Allow creating multiple NUMA sockets 2020-08-25 09:11:35 -07:00