qemu-e2k/target/arm
Peter Maydell 19b254e86a target/arm: Use correct SecuritySpace for AArch64 AT ops at EL3
When we do an AT address translation operation, the page table walk
is supposed to be performed in the context of the EL we're doing the
walk for, so for instance an AT S1E2R walk is done for EL2.  In the
pseudocode an EL is passed to AArch64.AT(), which calls
SecurityStateAtEL() to find the security state that we should be
doing the walk with.

In ats_write64() we get this wrong, instead using the current
security space always.  This is fine for AT operations performed from
EL1 and EL2, because there the current security state and the
security state for the lower EL are the same.  But for AT operations
performed from EL3, the current security state is always either
Secure or Root, whereas we want to use the security state defined by
SCR_EL3.{NS,NSE} for the walk. This affects not just guests using
FEAT_RME but also ones where EL3 is Secure state and the EL3 code
is trying to do an AT for a NonSecure EL2 or EL1.

Use arm_security_space_below_el3() to get the SecuritySpace to
pass to do_ats_write() for all AT operations except the
AT S1E3* operations.

Cc: qemu-stable@nongnu.org
Fixes: e1ee56ec23 ("target/arm: Pass security space rather than flag for AT instructions")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2250
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240405180232.3570066-1-peter.maydell@linaro.org
2024-04-08 15:38:53 +01:00
..
hvf accel/hvf: Un-inline hvf_arch_supports_guest_debug() 2024-04-02 14:55:32 +02:00
tcg target/arm: take HSTR traps of cp15 accesses to EL2, not EL1 2024-04-02 09:54:41 +01:00
arch_dump.c
arm-powerctl.c
arm-powerctl.h
arm-qmp-cmds.c target: Improve error reporting for CpuModelInfo member @props 2024-03-12 14:03:00 +01:00
common-semi-target.h
cortex-regs.c
cpregs.h
cpu64.c gdbstub: Infer number of core registers from XML 2024-02-28 09:09:58 +00:00
cpu-features.h target/arm: Implement FEAT_ECV CNTPOFF_EL2 handling 2024-03-07 12:19:03 +00:00
cpu-param.h target/arm: Enable TARGET_PAGE_BITS_VARY for AArch64 user-only 2024-02-29 11:35:37 -10:00
cpu-qom.h
cpu.c target: Replace CPU_GET_CLASS(cpu -> obj) in cpu_reset_hold() handler 2024-03-12 11:46:16 +01:00
cpu.h target/arm: Implement FEAT_ECV CNTPOFF_EL2 handling 2024-03-07 12:19:03 +00:00
debug_helper.c
gdbstub64.c gdbstub: Change gdb_get_reg_cb and gdb_set_reg_cb 2024-02-28 09:09:49 +00:00
gdbstub.c hw/core/cpu: Remove gdb_get_dynamic_xml member 2024-02-28 09:10:06 +00:00
gtimer.h
helper.c target/arm: Use correct SecuritySpace for AArch64 AT ops at EL3 2024-04-08 15:38:53 +01:00
helper.h
hvf_arm.h
hyp_gdbstub.c
idau.h
internals.h target/arm: use FIELD macro for CNTHCTL bit definitions 2024-03-07 12:19:01 +00:00
Kconfig
kvm_arm.h
kvm-consts.h
kvm-stub.c
kvm.c bulk: Access existing variables initialized to &S->F when available 2024-03-12 11:46:16 +01:00
machine.c bulk: Access existing variables initialized to &S->F when available 2024-03-12 11:46:16 +01:00
meson.build target/arm: Move v7m-related code from cpu32.c into a separate file 2024-03-08 14:45:03 +00:00
multiprocessing.h
op_addsub.h
ptw.c target/arm: Do memory type alignment check when translation enabled 2024-03-05 13:22:56 +00:00
syndrome.h
tcg-stubs.c
trace-events target/arm: Implement FEAT_ECV CNTPOFF_EL2 handling 2024-03-07 12:19:03 +00:00
trace.h
vfp_helper.c