Max Filippov eb3f4298c9 target/xtensa: implement PREFCTL SR ...

Cache prefetch option adds an unprivileged SR PREFCTL. Add trivial
implementation for this SR.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

2019-02-28 04:43:22 -08:00

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core-dc232b

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core-dc233c

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core-de212

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core-fsf

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core-sample_controller

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core-test_kc705_be

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core-test_mmuhifi_c3

target/xtensa: fixup test_mmuhifi_c3 overlay

2019-02-18 21:29:08 -08:00

core-dc232b.c

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core-dc233c.c

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core-de212.c

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core-fsf.c

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core-sample_controller.c

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core-test_kc705_be.c

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core-test_mmuhifi_c3.c

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cpu-qom.h

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cpu.c

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cpu.h

target/xtensa: implement PREFCTL SR

2019-02-28 04:43:22 -08:00

dbg_helper.c

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exc_helper.c

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fpu_helper.c

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gdbstub.c

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helper.c

target/xtensa: reorganize register handling in translators

2019-02-28 04:43:22 -08:00

helper.h

target/xtensa: only rotate window in the retw helper

2019-02-28 04:43:22 -08:00

import_core.sh

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Makefile.objs

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mmu_helper.c

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monitor.c

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op_helper.c

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overlay_tool.h

target/xtensa: move xtensa_finalize_config to xtensa_core_class_init

2019-02-18 21:29:08 -08:00

translate.c

target/xtensa: implement PREFCTL SR

2019-02-28 04:43:22 -08:00

win_helper.c

target/xtensa: only rotate window in the retw helper

2019-02-28 04:43:22 -08:00

xtensa-isa-internal.h

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xtensa-isa.c

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xtensa-isa.h

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xtensa-semi.c

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