Taylor Simpson 1e814a0dc4 Hexagon (target/hexagon) make VyV operands use a unique temp ... VyV operand is only used in the vshuff and vdeal instructions. These instructions write to both VyV and VxV operands. In the case where both operands are the same register, we need a separate location for VyV. We use the existing vtmp field in CPUHexagonState. Test case added in tests/tcg/hexagon/hvx_misc.c Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220718230320.24444-2-tsimpson@quicinc.com>		2022-07-31 16:22:09 -07:00
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alpha
arm	kvm: don't use perror() without useful errno	2022-07-29 00:15:02 +02:00
avr	target/avr: Drop avr_cpu_memory_rw_debug()	2022-06-20 13:11:36 -07:00
cris
hexagon	Hexagon (target/hexagon) make VyV operands use a unique temp	2022-07-31 16:22:09 -07:00
hppa
i386	hvf: Enable RDTSCP support	2022-07-13 00:05:39 +02:00
loongarch	hw/loongarch: Rename file 'loongson3.XXX' to 'virt.XXX'	2022-07-29 15:07:55 -07:00
m68k	target/m68k: Make semihosting system only	2022-06-28 10:13:22 +05:30
microblaze
mips	target/mips: Remove GET_TARGET_STRING and FREE_TARGET_STRING	2022-07-12 22:32:22 +02:00
nios2	target/nios2: Move nios2-semi.c to nios2_softmmu_ss	2022-06-28 10:18:57 +05:30
openrisc
ppc	target/ppc: Implement new wait variants	2022-07-28 13:30:41 -03:00
riscv	RISC-V: Allow both Zmmul and M	2022-07-27 17:34:02 +10:00
rx
s390x	target/s390x: fix handling of zeroes in vfmin/vfmax	2022-07-19 12:49:56 +02:00
sh4
sparc
tricore
xtensa
Kconfig	hw/loongarch: Add support loongson3 virt machine type.	2022-06-06 18:09:03 +00:00
meson.build	target/loongarch: Add target build suport	2022-06-06 18:09:03 +00:00